134 lines
4.0 KiB
C
134 lines
4.0 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "kfd_mqd_manager.h"
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#include "amdgpu_amdkfd.h"
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#include "kfd_device_queue_manager.h"
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/* Mapping queue priority to pipe priority, indexed by queue priority */
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int pipe_priority_map[] = {
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_LOW,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_MEDIUM,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH,
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KFD_PIPE_PRIORITY_CS_HIGH
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};
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struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_dev *dev, struct queue_properties *q)
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{
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struct kfd_mem_obj *mqd_mem_obj = NULL;
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mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
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if (!mqd_mem_obj)
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return NULL;
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mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem;
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mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr;
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mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr;
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return mqd_mem_obj;
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}
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struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_dev *dev,
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struct queue_properties *q)
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{
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struct kfd_mem_obj *mqd_mem_obj = NULL;
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uint64_t offset;
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mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
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if (!mqd_mem_obj)
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return NULL;
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offset = (q->sdma_engine_id *
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dev->device_info->num_sdma_queues_per_engine +
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q->sdma_queue_id) *
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dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size;
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offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
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mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem
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+ offset);
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mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
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mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)
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dev->dqm->hiq_sdma_mqd.cpu_ptr + offset);
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return mqd_mem_obj;
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}
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void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
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struct kfd_mem_obj *mqd_mem_obj)
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{
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WARN_ON(!mqd_mem_obj->gtt_mem);
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kfree(mqd_mem_obj);
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}
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void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
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const uint32_t *cu_mask, uint32_t cu_mask_count,
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uint32_t *se_mask)
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{
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struct kfd_cu_info cu_info;
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uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0};
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int i, se, sh, cu = 0;
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amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
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if (cu_mask_count > cu_info.cu_active_number)
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cu_mask_count = cu_info.cu_active_number;
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for (se = 0; se < cu_info.num_shader_engines; se++)
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for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
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cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
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/* Symmetrically map cu_mask to all SEs:
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* cu_mask[0] bit0 -> se_mask[0] bit0;
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* cu_mask[0] bit1 -> se_mask[1] bit0;
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* ... (if # SE is 4)
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* cu_mask[0] bit4 -> se_mask[0] bit1;
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* ...
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*/
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se = 0;
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for (i = 0; i < cu_mask_count; i++) {
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if (cu_mask[i / 32] & (1 << (i % 32)))
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se_mask[se] |= 1 << cu;
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do {
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se++;
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if (se == cu_info.num_shader_engines) {
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se = 0;
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cu++;
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}
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} while (cu >= cu_per_se[se] && cu < 32);
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}
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}
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