253 lines
7.0 KiB
C
253 lines
7.0 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v10_0.h"
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#include "mp/mp_10_0_offset.h"
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#include "gc/gc_9_1_offset.h"
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#include "sdma0/sdma0_4_1_offset.h"
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MODULE_FIRMWARE("amdgpu/raven_asd.bin");
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MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
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MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
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MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
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MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
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MODULE_FIRMWARE("amdgpu/raven_ta.bin");
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static int psp_v10_0_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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const char *chip_name;
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char fw_name[30];
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int err = 0;
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const struct ta_firmware_header_v1_0 *ta_hdr;
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DRM_DEBUG("\n");
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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if (adev->apu_flags & AMD_APU_IS_RAVEN2)
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chip_name = "raven2";
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else if (adev->apu_flags & AMD_APU_IS_PICASSO)
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chip_name = "picasso";
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else
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chip_name = "raven";
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break;
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default: BUG();
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}
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err = psp_init_asd_microcode(psp, chip_name);
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if (err)
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goto out;
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
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err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
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if (err) {
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release_firmware(adev->psp.ta_fw);
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adev->psp.ta_fw = NULL;
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dev_info(adev->dev,
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"psp v10.0: Failed to load firmware \"%s\"\n",
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fw_name);
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} else {
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err = amdgpu_ucode_validate(adev->psp.ta_fw);
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if (err)
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goto out2;
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ta_hdr = (const struct ta_firmware_header_v1_0 *)
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adev->psp.ta_fw->data;
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adev->psp.ta_hdcp_ucode_version =
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le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
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adev->psp.ta_hdcp_ucode_size =
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le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
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adev->psp.ta_hdcp_start_addr =
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(uint8_t *)ta_hdr +
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le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
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adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
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adev->psp.ta_dtm_ucode_version =
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le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
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adev->psp.ta_dtm_ucode_size =
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le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
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adev->psp.ta_dtm_start_addr =
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(uint8_t *)adev->psp.ta_hdcp_start_addr +
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le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
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}
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return 0;
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out2:
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release_firmware(adev->psp.ta_fw);
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adev->psp.ta_fw = NULL;
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out:
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if (err) {
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dev_err(adev->dev,
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"psp v10.0: Failed to load firmware \"%s\"\n",
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fw_name);
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}
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return err;
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}
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static int psp_v10_0_ring_init(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring;
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struct amdgpu_device *adev = psp->adev;
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ring = &psp->km_ring;
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ring->ring_type = ring_type;
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/* allocate 4k Page of Local Frame Buffer memory for ring */
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ring->ring_size = 0x1000;
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ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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if (ret) {
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ring->ring_size = 0;
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return ret;
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}
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return 0;
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}
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static int psp_v10_0_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* There might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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return ret;
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}
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static int psp_v10_0_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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/* Write the ring destroy command to C2PMSG_64 */
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psp_ring_reg = 3 << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* There might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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return ret;
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}
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static int psp_v10_0_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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ret = psp_v10_0_ring_stop(psp, ring_type);
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if (ret)
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DRM_ERROR("Fail to stop psp ring\n");
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amdgpu_bo_free_kernel(&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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return ret;
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}
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static int psp_v10_0_mode1_reset(struct psp_context *psp)
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{
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DRM_INFO("psp mode 1 reset not supported now! \n");
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return -EINVAL;
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}
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static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
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}
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static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
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{
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struct amdgpu_device *adev = psp->adev;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
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}
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static const struct psp_funcs psp_v10_0_funcs = {
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.init_microcode = psp_v10_0_init_microcode,
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.ring_init = psp_v10_0_ring_init,
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.ring_create = psp_v10_0_ring_create,
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.ring_stop = psp_v10_0_ring_stop,
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.ring_destroy = psp_v10_0_ring_destroy,
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.mode1_reset = psp_v10_0_mode1_reset,
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.ring_get_wptr = psp_v10_0_ring_get_wptr,
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.ring_set_wptr = psp_v10_0_ring_set_wptr,
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};
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void psp_v10_0_set_psp_funcs(struct psp_context *psp)
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{
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psp->funcs = &psp_v10_0_funcs;
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}
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