John Crispin 61fa969f27 MIPS: lantiq: split up IRQ IM ranges ... Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate the SVIP we need to support IM ranges that are scattered inside the register range. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4237/		2012-08-23 00:08:17 +02:00
..
asm	MIPS: lantiq: split up IRQ IM ranges	2012-08-23 00:08:17 +02:00