150 lines
3.8 KiB
C
150 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm SDX55 APCS clock controller driver
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*
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* Copyright (c) 2020, Linaro Limited
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/cpu.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "clk-regmap.h"
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#include "clk-regmap-mux-div.h"
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static const u32 apcs_mux_clk_parent_map[] = { 0, 1, 5 };
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static const struct clk_parent_data pdata[] = {
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{ .fw_name = "ref" },
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{ .fw_name = "aux" },
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{ .fw_name = "pll" },
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};
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/*
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* We use the notifier function for switching to a temporary safe configuration
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* (mux and divider), while the A7 PLL is reconfigured.
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*/
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static int a7cc_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data)
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{
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int ret = 0;
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struct clk_regmap_mux_div *md = container_of(nb,
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struct clk_regmap_mux_div,
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clk_nb);
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if (event == PRE_RATE_CHANGE)
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/* set the mux and divider to safe frequency (400mhz) */
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ret = mux_div_set_src_div(md, 1, 2);
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return notifier_from_errno(ret);
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}
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static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device *parent = dev->parent;
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struct device *cpu_dev;
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struct clk_regmap_mux_div *a7cc;
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struct regmap *regmap;
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struct clk_init_data init = { };
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int ret;
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regmap = dev_get_regmap(parent, NULL);
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if (!regmap) {
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dev_err_probe(dev, -ENODEV, "Failed to get parent regmap\n");
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return -ENODEV;
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}
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a7cc = devm_kzalloc(dev, sizeof(*a7cc), GFP_KERNEL);
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if (!a7cc)
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return -ENOMEM;
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init.name = "a7mux";
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init.parent_data = pdata;
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init.num_parents = ARRAY_SIZE(pdata);
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init.ops = &clk_regmap_mux_div_ops;
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a7cc->clkr.hw.init = &init;
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a7cc->clkr.regmap = regmap;
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a7cc->reg_offset = 0x8;
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a7cc->hid_width = 5;
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a7cc->hid_shift = 0;
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a7cc->src_width = 3;
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a7cc->src_shift = 8;
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a7cc->parent_map = apcs_mux_clk_parent_map;
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a7cc->pclk = devm_clk_get(parent, "pll");
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if (IS_ERR(a7cc->pclk)) {
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ret = PTR_ERR(a7cc->pclk);
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if (ret != -EPROBE_DEFER)
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dev_err_probe(dev, ret, "Failed to get PLL clk\n");
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return ret;
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}
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a7cc->clk_nb.notifier_call = a7cc_notifier_cb;
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ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb);
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if (ret) {
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dev_err_probe(dev, ret, "Failed to register clock notifier\n");
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return ret;
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}
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ret = devm_clk_register_regmap(dev, &a7cc->clkr);
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if (ret) {
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dev_err_probe(dev, ret, "Failed to register regmap clock\n");
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goto err;
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
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&a7cc->clkr.hw);
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if (ret) {
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dev_err_probe(dev, ret, "Failed to add clock provider\n");
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goto err;
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}
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platform_set_drvdata(pdev, a7cc);
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/*
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* Attach the power domain to cpudev. Since there is no dedicated driver
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* for CPUs and the SDX55 platform lacks hardware specific CPUFreq
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* driver, there seems to be no better place to do this. So do it here!
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*/
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cpu_dev = get_cpu_device(0);
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dev_pm_domain_attach(cpu_dev, true);
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return 0;
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err:
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clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
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return ret;
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}
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static int qcom_apcs_sdx55_clk_remove(struct platform_device *pdev)
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{
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struct device *cpu_dev = get_cpu_device(0);
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struct clk_regmap_mux_div *a7cc = platform_get_drvdata(pdev);
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clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
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dev_pm_domain_detach(cpu_dev, true);
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return 0;
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}
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static struct platform_driver qcom_apcs_sdx55_clk_driver = {
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.probe = qcom_apcs_sdx55_clk_probe,
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.remove = qcom_apcs_sdx55_clk_remove,
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.driver = {
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.name = "qcom-sdx55-acps-clk",
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},
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};
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module_platform_driver(qcom_apcs_sdx55_clk_driver);
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MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Qualcomm SDX55 APCS clock driver");
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