405 lines
11 KiB
C
405 lines
11 KiB
C
/*
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* Copyright (c) 2016 Hisilicon Limited.
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* Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/platform_device.h>
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#include "hns_roce_device.h"
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#include "hns_roce_hem.h"
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#include "hns_roce_common.h"
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#define HNS_ROCE_HEM_ALLOC_SIZE (1 << 17)
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#define HNS_ROCE_TABLE_CHUNK_SIZE (1 << 17)
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#define DMA_ADDR_T_SHIFT 12
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#define BT_BA_SHIFT 32
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struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, int npages,
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gfp_t gfp_mask)
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{
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struct hns_roce_hem_chunk *chunk = NULL;
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struct hns_roce_hem *hem;
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struct scatterlist *mem;
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int order;
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void *buf;
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WARN_ON(gfp_mask & __GFP_HIGHMEM);
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hem = kmalloc(sizeof(*hem),
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gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
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if (!hem)
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return NULL;
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hem->refcount = 0;
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INIT_LIST_HEAD(&hem->chunk_list);
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order = get_order(HNS_ROCE_HEM_ALLOC_SIZE);
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while (npages > 0) {
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if (!chunk) {
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chunk = kmalloc(sizeof(*chunk),
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gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
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if (!chunk)
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goto fail;
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sg_init_table(chunk->mem, HNS_ROCE_HEM_CHUNK_LEN);
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chunk->npages = 0;
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chunk->nsg = 0;
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list_add_tail(&chunk->list, &hem->chunk_list);
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}
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while (1 << order > npages)
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--order;
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/*
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* Alloc memory one time. If failed, don't alloc small block
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* memory, directly return fail.
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*/
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mem = &chunk->mem[chunk->npages];
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buf = dma_alloc_coherent(&hr_dev->pdev->dev, PAGE_SIZE << order,
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&sg_dma_address(mem), gfp_mask);
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if (!buf)
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goto fail;
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sg_set_buf(mem, buf, PAGE_SIZE << order);
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WARN_ON(mem->offset);
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sg_dma_len(mem) = PAGE_SIZE << order;
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++chunk->npages;
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++chunk->nsg;
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npages -= 1 << order;
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}
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return hem;
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fail:
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hns_roce_free_hem(hr_dev, hem);
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return NULL;
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}
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void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
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{
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struct hns_roce_hem_chunk *chunk, *tmp;
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int i;
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if (!hem)
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return;
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list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) {
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for (i = 0; i < chunk->npages; ++i)
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dma_free_coherent(&hr_dev->pdev->dev,
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chunk->mem[i].length,
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lowmem_page_address(sg_page(&chunk->mem[i])),
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sg_dma_address(&chunk->mem[i]));
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kfree(chunk);
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}
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kfree(hem);
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}
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static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, unsigned long obj)
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{
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struct device *dev = &hr_dev->pdev->dev;
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spinlock_t *lock = &hr_dev->bt_cmd_lock;
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unsigned long end = 0;
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unsigned long flags;
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struct hns_roce_hem_iter iter;
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void __iomem *bt_cmd;
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u32 bt_cmd_h_val = 0;
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u32 bt_cmd_val[2];
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u32 bt_cmd_l = 0;
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u64 bt_ba = 0;
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int ret = 0;
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/* Find the HEM(Hardware Entry Memory) entry */
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unsigned long i = (obj & (table->num_obj - 1)) /
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(HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size);
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switch (table->type) {
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case HEM_TYPE_QPC:
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roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
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break;
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case HEM_TYPE_MTPT:
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roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S,
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HEM_TYPE_MTPT);
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break;
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case HEM_TYPE_CQC:
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roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
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break;
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case HEM_TYPE_SRQC:
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roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S,
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HEM_TYPE_SRQC);
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break;
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default:
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return ret;
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}
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roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
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roce_set_bit(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
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roce_set_bit(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
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/* Currently iter only a chunk */
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for (hns_roce_hem_first(table->hem[i], &iter);
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!hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
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bt_ba = hns_roce_hem_addr(&iter) >> DMA_ADDR_T_SHIFT;
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spin_lock_irqsave(lock, flags);
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bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
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end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
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while (1) {
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if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
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if (!(time_before(jiffies, end))) {
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dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
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spin_unlock_irqrestore(lock, flags);
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return -EBUSY;
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}
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} else {
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break;
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}
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msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
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}
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bt_cmd_l = (u32)bt_ba;
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roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
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ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
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bt_ba >> BT_BA_SHIFT);
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bt_cmd_val[0] = bt_cmd_l;
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bt_cmd_val[1] = bt_cmd_h_val;
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hns_roce_write64_k(bt_cmd_val,
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hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
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spin_unlock_irqrestore(lock, flags);
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}
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return ret;
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}
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int hns_roce_table_get(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, unsigned long obj)
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{
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struct device *dev = &hr_dev->pdev->dev;
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int ret = 0;
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unsigned long i;
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i = (obj & (table->num_obj - 1)) / (HNS_ROCE_TABLE_CHUNK_SIZE /
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table->obj_size);
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mutex_lock(&table->mutex);
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if (table->hem[i]) {
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++table->hem[i]->refcount;
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goto out;
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}
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table->hem[i] = hns_roce_alloc_hem(hr_dev,
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HNS_ROCE_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
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(table->lowmem ? GFP_KERNEL :
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GFP_HIGHUSER) | __GFP_NOWARN);
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if (!table->hem[i]) {
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ret = -ENOMEM;
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goto out;
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}
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/* Set HEM base address(128K/page, pa) to Hardware */
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if (hns_roce_set_hem(hr_dev, table, obj)) {
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ret = -ENODEV;
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dev_err(dev, "set HEM base address to HW failed.\n");
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goto out;
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}
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++table->hem[i]->refcount;
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out:
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mutex_unlock(&table->mutex);
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return ret;
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}
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void hns_roce_table_put(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, unsigned long obj)
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{
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struct device *dev = &hr_dev->pdev->dev;
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unsigned long i;
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i = (obj & (table->num_obj - 1)) /
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(HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size);
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mutex_lock(&table->mutex);
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if (--table->hem[i]->refcount == 0) {
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/* Clear HEM base address */
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if (hr_dev->hw->clear_hem(hr_dev, table, obj))
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dev_warn(dev, "Clear HEM base address failed.\n");
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hns_roce_free_hem(hr_dev, table->hem[i]);
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table->hem[i] = NULL;
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}
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mutex_unlock(&table->mutex);
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}
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void *hns_roce_table_find(struct hns_roce_hem_table *table, unsigned long obj,
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dma_addr_t *dma_handle)
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{
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struct hns_roce_hem_chunk *chunk;
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unsigned long idx;
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int i;
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int offset, dma_offset;
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struct hns_roce_hem *hem;
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struct page *page = NULL;
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if (!table->lowmem)
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return NULL;
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mutex_lock(&table->mutex);
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idx = (obj & (table->num_obj - 1)) * table->obj_size;
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hem = table->hem[idx / HNS_ROCE_TABLE_CHUNK_SIZE];
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dma_offset = offset = idx % HNS_ROCE_TABLE_CHUNK_SIZE;
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if (!hem)
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goto out;
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list_for_each_entry(chunk, &hem->chunk_list, list) {
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for (i = 0; i < chunk->npages; ++i) {
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if (dma_handle && dma_offset >= 0) {
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if (sg_dma_len(&chunk->mem[i]) >
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(u32)dma_offset)
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*dma_handle = sg_dma_address(
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&chunk->mem[i]) + dma_offset;
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dma_offset -= sg_dma_len(&chunk->mem[i]);
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}
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if (chunk->mem[i].length > (u32)offset) {
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page = sg_page(&chunk->mem[i]);
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goto out;
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}
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offset -= chunk->mem[i].length;
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}
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}
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out:
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mutex_unlock(&table->mutex);
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return page ? lowmem_page_address(page) + offset : NULL;
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}
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int hns_roce_table_get_range(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table,
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unsigned long start, unsigned long end)
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{
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unsigned long inc = HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size;
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unsigned long i = 0;
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int ret = 0;
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/* Allocate MTT entry memory according to chunk(128K) */
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for (i = start; i <= end; i += inc) {
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ret = hns_roce_table_get(hr_dev, table, i);
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if (ret)
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goto fail;
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}
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return 0;
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fail:
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while (i > start) {
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i -= inc;
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hns_roce_table_put(hr_dev, table, i);
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}
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return ret;
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}
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void hns_roce_table_put_range(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table,
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unsigned long start, unsigned long end)
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{
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unsigned long i;
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for (i = start; i <= end;
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i += HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size)
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hns_roce_table_put(hr_dev, table, i);
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}
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int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table, u32 type,
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unsigned long obj_size, unsigned long nobj,
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int use_lowmem)
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{
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unsigned long obj_per_chunk;
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unsigned long num_hem;
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obj_per_chunk = HNS_ROCE_TABLE_CHUNK_SIZE / obj_size;
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num_hem = (nobj + obj_per_chunk - 1) / obj_per_chunk;
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table->hem = kcalloc(num_hem, sizeof(*table->hem), GFP_KERNEL);
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if (!table->hem)
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return -ENOMEM;
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table->type = type;
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table->num_hem = num_hem;
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table->num_obj = nobj;
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table->obj_size = obj_size;
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table->lowmem = use_lowmem;
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mutex_init(&table->mutex);
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return 0;
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}
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void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
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struct hns_roce_hem_table *table)
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{
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struct device *dev = &hr_dev->pdev->dev;
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unsigned long i;
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for (i = 0; i < table->num_hem; ++i)
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if (table->hem[i]) {
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if (hr_dev->hw->clear_hem(hr_dev, table,
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i * HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size))
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dev_err(dev, "Clear HEM base address failed.\n");
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hns_roce_free_hem(hr_dev, table->hem[i]);
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}
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kfree(table->hem);
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}
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void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev)
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{
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hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
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hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
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hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
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hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
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hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
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}
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