83 lines
3.4 KiB
Plaintext
83 lines
3.4 KiB
Plaintext
TI AM654 SERDES
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Required properties:
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- compatible: Should be "ti,phy-am654-serdes"
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- reg : Address and length of the register set for the device.
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- #phy-cells: determine the number of cells that should be given in the
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phandle while referencing this phy. Should be "2". The 1st cell
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corresponds to the phy type (should be one of the types specified in
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include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
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lane function.
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If SERDES0 is referenced 2nd cell should be:
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0 - USB3
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1 - PCIe0 Lane0
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2 - ICSS2 SGMII Lane0
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If SERDES1 is referenced 2nd cell should be:
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0 - PCIe1 Lane0
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1 - PCIe0 Lane1
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2 - ICSS2 SGMII Lane1
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- power-domains: As documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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- clocks: List of clock-specifiers representing the input to the SERDES.
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Should have 3 items representing the left input clock, external
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reference clock and right input clock in that order.
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- clock-output-names: List of clock names for each of the clock outputs of
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SERDES. Should have 3 items for CMU reference clock,
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left output clock and right output clock in that order.
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- assigned-clocks: As defined in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- assigned-clock-parents: As defined in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- #clock-cells: Should be <1> to choose between the 3 output clocks.
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Defined in Documentation/devicetree/bindings/clock/clock-bindings.txt
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The following macros are defined in dt-bindings/phy/phy-am654-serdes.h
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for selecting the correct reference clock. This can be used while
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specifying the clocks created by SERDES.
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=> AM654_SERDES_CMU_REFCLK
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=> AM654_SERDES_LO_REFCLK
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=> AM654_SERDES_RO_REFCLK
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- mux-controls: Phandle to the multiplexer that is used to select the lane
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function. See #phy-cells above to see the multiplex values.
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Example:
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Example for SERDES0 is given below. It has 3 clock inputs;
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left input reference clock as indicated by <&k3_clks 153 4>, external
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reference clock as indicated by <&k3_clks 153 1> and right input
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reference clock as indicated by <&serdes1 AM654_SERDES_LO_REFCLK>. (The
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right input of SERDES0 is connected to the left output of SERDES1).
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SERDES0 registers 3 clock outputs as indicated in clock-output-names. The
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first refers to the CMU reference clock, second refers to the left output
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reference clock and the third refers to the right output reference clock.
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The assigned-clocks and assigned-clock-parents is used here to set the
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parent of left input reference clock to MAINHSDIV_CLKOUT4 and parent of
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CMU reference clock to left input reference clock.
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serdes0: serdes@900000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x900000 0x0 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
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power-domains = <&k3_pds 153>;
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clocks = <&k3_clks 153 4>, <&k3_clks 153 1>,
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<&serdes1 AM654_SERDES_LO_REFCLK>;
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clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk",
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"serdes0_ro_refclk";
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assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
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ti,serdes-clk = <&serdes0_clk>;
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mux-controls = <&serdes_mux 0>;
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#clock-cells = <1>;
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};
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Example for PCIe consumer node using the SERDES PHY specifier is given below.
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&pcie0_rc {
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num-lanes = <2>;
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phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
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phy-names = "pcie-phy0", "pcie-phy1";
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};
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