304 lines
6.0 KiB
C
304 lines
6.0 KiB
C
/*
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* Architecture specific OF callbacks.
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*/
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#include <linux/bootmem.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/of_pci.h>
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#include <linux/initrd.h>
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#include <asm/irqdomain.h>
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#include <asm/hpet.h>
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#include <asm/apic.h>
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#include <asm/pci_x86.h>
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#include <asm/setup.h>
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#include <asm/i8259.h>
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__initdata u64 initial_dtb;
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char __initdata cmd_line[COMMAND_LINE_SIZE];
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int __initdata of_ioapic;
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void __init early_init_dt_scan_chosen_arch(unsigned long node)
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{
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BUG();
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}
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void __init early_init_dt_add_memory_arch(u64 base, u64 size)
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{
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BUG();
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}
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void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
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{
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return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
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}
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void __init add_dtb(u64 data)
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{
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initial_dtb = data + offsetof(struct setup_data, data);
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}
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/*
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* CE4100 ids. Will be moved to machine_device_initcall() once we have it.
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*/
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static struct of_device_id __initdata ce4100_ids[] = {
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{ .compatible = "intel,ce4100-cp", },
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{ .compatible = "isa", },
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{ .compatible = "pci", },
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{},
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};
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static int __init add_bus_probe(void)
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{
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if (!of_have_populated_dt())
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return 0;
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return of_platform_bus_probe(NULL, ce4100_ids, NULL);
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}
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device_initcall(add_bus_probe);
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#ifdef CONFIG_PCI
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struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
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{
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struct device_node *np;
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for_each_node_by_type(np, "pci") {
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const void *prop;
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unsigned int bus_min;
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prop = of_get_property(np, "bus-range", NULL);
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if (!prop)
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continue;
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bus_min = be32_to_cpup(prop);
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if (bus->number == bus_min)
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return np;
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}
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return NULL;
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}
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static int x86_of_pci_irq_enable(struct pci_dev *dev)
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{
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u32 virq;
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int ret;
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u8 pin;
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ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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if (ret)
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return ret;
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if (!pin)
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return 0;
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virq = of_irq_parse_and_map_pci(dev, 0, 0);
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if (virq == 0)
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return -EINVAL;
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dev->irq = virq;
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return 0;
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}
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static void x86_of_pci_irq_disable(struct pci_dev *dev)
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{
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}
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void x86_of_pci_init(void)
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{
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pcibios_enable_irq = x86_of_pci_irq_enable;
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pcibios_disable_irq = x86_of_pci_irq_disable;
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}
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#endif
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static void __init dtb_setup_hpet(void)
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{
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#ifdef CONFIG_HPET_TIMER
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struct device_node *dn;
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struct resource r;
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int ret;
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dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
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if (!dn)
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return;
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ret = of_address_to_resource(dn, 0, &r);
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if (ret) {
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WARN_ON(1);
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return;
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}
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hpet_address = r.start;
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#endif
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}
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static void __init dtb_lapic_setup(void)
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{
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#ifdef CONFIG_X86_LOCAL_APIC
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struct device_node *dn;
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struct resource r;
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int ret;
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dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
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if (!dn)
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return;
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ret = of_address_to_resource(dn, 0, &r);
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if (WARN_ON(ret))
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return;
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/* Did the boot loader setup the local APIC ? */
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if (!boot_cpu_has(X86_FEATURE_APIC)) {
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if (apic_force_enable(r.start))
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return;
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}
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smp_found_config = 1;
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pic_mode = 1;
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register_lapic_address(r.start);
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generic_processor_info(boot_cpu_physical_apicid,
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GET_APIC_VERSION(apic_read(APIC_LVR)));
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#endif
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}
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#ifdef CONFIG_X86_IO_APIC
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static unsigned int ioapic_id;
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struct of_ioapic_type {
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u32 out_type;
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u32 trigger;
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u32 polarity;
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};
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static struct of_ioapic_type of_ioapic_type[] =
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{
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{
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.out_type = IRQ_TYPE_EDGE_RISING,
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.trigger = IOAPIC_EDGE,
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.polarity = 1,
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},
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{
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.out_type = IRQ_TYPE_LEVEL_LOW,
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.trigger = IOAPIC_LEVEL,
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.polarity = 0,
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},
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{
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.out_type = IRQ_TYPE_LEVEL_HIGH,
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.trigger = IOAPIC_LEVEL,
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.polarity = 1,
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},
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{
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.out_type = IRQ_TYPE_EDGE_FALLING,
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.trigger = IOAPIC_EDGE,
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.polarity = 0,
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},
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};
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static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct of_phandle_args *irq_data = (void *)arg;
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struct of_ioapic_type *it;
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struct irq_alloc_info tmp;
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if (WARN_ON(irq_data->args_count < 2))
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return -EINVAL;
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if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
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return -EINVAL;
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it = &of_ioapic_type[irq_data->args[1]];
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ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
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tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
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tmp.ioapic_pin = irq_data->args[0];
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return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
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}
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static const struct irq_domain_ops ioapic_irq_domain_ops = {
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.alloc = dt_irqdomain_alloc,
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.free = mp_irqdomain_free,
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.activate = mp_irqdomain_activate,
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.deactivate = mp_irqdomain_deactivate,
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};
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static void __init dtb_add_ioapic(struct device_node *dn)
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{
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struct resource r;
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int ret;
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struct ioapic_domain_cfg cfg = {
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.type = IOAPIC_DOMAIN_DYNAMIC,
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.ops = &ioapic_irq_domain_ops,
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.dev = dn,
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};
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ret = of_address_to_resource(dn, 0, &r);
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if (ret) {
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printk(KERN_ERR "Can't obtain address from node %s.\n",
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dn->full_name);
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return;
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}
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mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
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}
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static void __init dtb_ioapic_setup(void)
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{
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struct device_node *dn;
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for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
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dtb_add_ioapic(dn);
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if (nr_ioapics) {
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of_ioapic = 1;
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return;
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}
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printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
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}
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#else
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static void __init dtb_ioapic_setup(void) {}
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#endif
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static void __init dtb_apic_setup(void)
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{
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dtb_lapic_setup();
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dtb_ioapic_setup();
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}
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#ifdef CONFIG_OF_FLATTREE
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static void __init x86_flattree_get_config(void)
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{
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u32 size, map_len;
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void *dt;
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if (!initial_dtb)
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return;
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map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
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initial_boot_params = dt = early_memremap(initial_dtb, map_len);
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size = of_get_flat_dt_size();
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if (map_len < size) {
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early_memunmap(dt, map_len);
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initial_boot_params = dt = early_memremap(initial_dtb, size);
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map_len = size;
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}
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unflatten_and_copy_device_tree();
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early_memunmap(dt, map_len);
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}
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#else
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static inline void x86_flattree_get_config(void) { }
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#endif
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void __init x86_dtb_init(void)
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{
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x86_flattree_get_config();
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if (!of_have_populated_dt())
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return;
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dtb_setup_hpet();
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dtb_apic_setup();
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}
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