329 lines
10 KiB
C
329 lines
10 KiB
C
/*
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* Marvell Wireless LAN device driver: SDIO specific definitions
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*
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* Copyright (C) 2011, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*/
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#ifndef _MWIFIEX_SDIO_H
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#define _MWIFIEX_SDIO_H
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/sdio_ids.h>
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#include <linux/mmc/sdio_func.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include "main.h"
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#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
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#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
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#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
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#define BLOCK_MODE 1
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#define BYTE_MODE 0
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#define REG_PORT 0
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#define RD_BITMAP_L 0x04
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#define RD_BITMAP_U 0x05
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#define WR_BITMAP_L 0x06
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#define WR_BITMAP_U 0x07
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#define RD_LEN_P0_L 0x08
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#define RD_LEN_P0_U 0x09
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#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
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#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
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#define CTRL_PORT 0
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#define CTRL_PORT_MASK 0x0001
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#define DATA_PORT_MASK 0xfffe
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#define MAX_MP_REGS 64
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#define MAX_PORT 16
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#define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
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#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
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/* Multi port RX aggregation buffer size */
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#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
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/* Misc. Config Register : Auto Re-enable interrupts */
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#define AUTO_RE_ENABLE_INT BIT(4)
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/* Host Control Registers */
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/* Host Control Registers : I/O port 0 */
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#define IO_PORT_0_REG 0x78
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/* Host Control Registers : I/O port 1 */
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#define IO_PORT_1_REG 0x79
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/* Host Control Registers : I/O port 2 */
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#define IO_PORT_2_REG 0x7A
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/* Host Control Registers : Configuration */
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#define CONFIGURATION_REG 0x00
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/* Host Control Registers : Host without Command 53 finish host*/
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#define HOST_TO_CARD_EVENT (0x1U << 3)
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/* Host Control Registers : Host without Command 53 finish host */
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#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
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/* Host Control Registers : Host power up */
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#define HOST_POWER_UP (0x1U << 1)
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/* Host Control Registers : Host power down */
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#define HOST_POWER_DOWN (0x1U << 0)
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/* Host Control Registers : Host interrupt mask */
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#define HOST_INT_MASK_REG 0x02
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/* Host Control Registers : Upload host interrupt mask */
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#define UP_LD_HOST_INT_MASK (0x1U)
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/* Host Control Registers : Download host interrupt mask */
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#define DN_LD_HOST_INT_MASK (0x2U)
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/* Enable Host interrupt mask */
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#define HOST_INT_ENABLE (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK)
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/* Disable Host interrupt mask */
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#define HOST_INT_DISABLE 0xff
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/* Host Control Registers : Host interrupt status */
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#define HOST_INTSTATUS_REG 0x03
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/* Host Control Registers : Upload host interrupt status */
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#define UP_LD_HOST_INT_STATUS (0x1U)
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/* Host Control Registers : Download host interrupt status */
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#define DN_LD_HOST_INT_STATUS (0x2U)
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/* Host Control Registers : Host interrupt RSR */
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#define HOST_INT_RSR_REG 0x01
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/* Host Control Registers : Upload host interrupt RSR */
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#define UP_LD_HOST_INT_RSR (0x1U)
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#define SDIO_INT_MASK 0x3F
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/* Host Control Registers : Host interrupt status */
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#define HOST_INT_STATUS_REG 0x28
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/* Host Control Registers : Upload CRC error */
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#define UP_LD_CRC_ERR (0x1U << 2)
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/* Host Control Registers : Upload restart */
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#define UP_LD_RESTART (0x1U << 1)
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/* Host Control Registers : Download restart */
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#define DN_LD_RESTART (0x1U << 0)
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/* Card Control Registers : Card status register */
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#define CARD_STATUS_REG 0x30
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/* Card Control Registers : Card I/O ready */
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#define CARD_IO_READY (0x1U << 3)
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/* Card Control Registers : CIS card ready */
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#define CIS_CARD_RDY (0x1U << 2)
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/* Card Control Registers : Upload card ready */
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#define UP_LD_CARD_RDY (0x1U << 1)
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/* Card Control Registers : Download card ready */
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#define DN_LD_CARD_RDY (0x1U << 0)
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/* Card Control Registers : Host interrupt mask register */
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#define HOST_INTERRUPT_MASK_REG 0x34
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/* Card Control Registers : Host power interrupt mask */
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#define HOST_POWER_INT_MASK (0x1U << 3)
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/* Card Control Registers : Abort card interrupt mask */
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#define ABORT_CARD_INT_MASK (0x1U << 2)
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/* Card Control Registers : Upload card interrupt mask */
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#define UP_LD_CARD_INT_MASK (0x1U << 1)
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/* Card Control Registers : Download card interrupt mask */
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#define DN_LD_CARD_INT_MASK (0x1U << 0)
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/* Card Control Registers : Card interrupt status register */
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#define CARD_INTERRUPT_STATUS_REG 0x38
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/* Card Control Registers : Power up interrupt */
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#define POWER_UP_INT (0x1U << 4)
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/* Card Control Registers : Power down interrupt */
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#define POWER_DOWN_INT (0x1U << 3)
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/* Card Control Registers : Card interrupt RSR register */
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#define CARD_INTERRUPT_RSR_REG 0x3c
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/* Card Control Registers : Power up RSR */
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#define POWER_UP_RSR (0x1U << 4)
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/* Card Control Registers : Power down RSR */
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#define POWER_DOWN_RSR (0x1U << 3)
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/* Card Control Registers : Miscellaneous Configuration Register */
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#define CARD_MISC_CFG_REG 0x6C
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/* Host F1 read base 0 */
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#define HOST_F1_RD_BASE_0 0x0040
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/* Host F1 read base 1 */
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#define HOST_F1_RD_BASE_1 0x0041
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/* Host F1 card ready */
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#define HOST_F1_CARD_RDY 0x0020
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/* Firmware status 0 register */
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#define CARD_FW_STATUS0_REG 0x60
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/* Firmware status 1 register */
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#define CARD_FW_STATUS1_REG 0x61
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/* Rx length register */
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#define CARD_RX_LEN_REG 0x62
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/* Rx unit register */
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#define CARD_RX_UNIT_REG 0x63
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/* Max retry number of CMD53 write */
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#define MAX_WRITE_IOMEM_RETRY 2
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/* SDIO Tx aggregation in progress ? */
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#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
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/* SDIO Tx aggregation buffer room for next packet ? */
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#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
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<= a->mpa_tx.buf_size)
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/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
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#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
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memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
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payload, pkt_len); \
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a->mpa_tx.buf_len += pkt_len; \
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if (!a->mpa_tx.pkt_cnt) \
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a->mpa_tx.start_port = port; \
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if (a->mpa_tx.start_port <= port) \
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a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
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else \
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a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+(MAX_PORT - \
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a->mp_end_port))); \
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a->mpa_tx.pkt_cnt++; \
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} while (0)
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/* SDIO Tx aggregation limit ? */
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#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
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(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
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/* SDIO Tx aggregation port limit ? */
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#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port < \
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a->mpa_tx.start_port) && (((MAX_PORT - \
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a->mpa_tx.start_port) + a->curr_wr_port) >= \
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SDIO_MP_AGGR_DEF_PKT_LIMIT))
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/* Reset SDIO Tx aggregation buffer parameters */
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#define MP_TX_AGGR_BUF_RESET(a) do { \
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a->mpa_tx.pkt_cnt = 0; \
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a->mpa_tx.buf_len = 0; \
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a->mpa_tx.ports = 0; \
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a->mpa_tx.start_port = 0; \
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} while (0)
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/* SDIO Rx aggregation limit ? */
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#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
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(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
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/* SDIO Tx aggregation port limit ? */
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#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port < \
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a->mpa_rx.start_port) && (((MAX_PORT - \
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a->mpa_rx.start_port) + a->curr_rd_port) >= \
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SDIO_MP_AGGR_DEF_PKT_LIMIT))
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/* SDIO Rx aggregation in progress ? */
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#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
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/* SDIO Rx aggregation buffer room for next packet ? */
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#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
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((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
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/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
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#define MP_RX_AGGR_SETUP(a, skb, port) do { \
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a->mpa_rx.buf_len += skb->len; \
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if (!a->mpa_rx.pkt_cnt) \
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a->mpa_rx.start_port = port; \
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if (a->mpa_rx.start_port <= port) \
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a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt)); \
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else \
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a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt+1)); \
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a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb; \
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a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len; \
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a->mpa_rx.pkt_cnt++; \
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} while (0)
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/* Reset SDIO Rx aggregation buffer parameters */
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#define MP_RX_AGGR_BUF_RESET(a) do { \
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a->mpa_rx.pkt_cnt = 0; \
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a->mpa_rx.buf_len = 0; \
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a->mpa_rx.ports = 0; \
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a->mpa_rx.start_port = 0; \
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} while (0)
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/* data structure for SDIO MPA TX */
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struct mwifiex_sdio_mpa_tx {
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/* multiport tx aggregation buffer pointer */
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u8 *buf;
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u32 buf_len;
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u32 pkt_cnt;
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u16 ports;
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u16 start_port;
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u8 enabled;
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u32 buf_size;
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u32 pkt_aggr_limit;
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};
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struct mwifiex_sdio_mpa_rx {
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u8 *buf;
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u32 buf_len;
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u32 pkt_cnt;
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u16 ports;
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u16 start_port;
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struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
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u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
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u8 enabled;
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u32 buf_size;
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u32 pkt_aggr_limit;
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};
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int mwifiex_bus_register(void);
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void mwifiex_bus_unregister(void);
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struct sdio_mmc_card {
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struct sdio_func *func;
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struct mwifiex_adapter *adapter;
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u16 mp_rd_bitmap;
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u16 mp_wr_bitmap;
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u16 mp_end_port;
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u16 mp_data_port_mask;
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u8 curr_rd_port;
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u8 curr_wr_port;
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u8 *mp_regs;
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struct mwifiex_sdio_mpa_tx mpa_tx;
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struct mwifiex_sdio_mpa_rx mpa_rx;
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};
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/*
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* .cmdrsp_complete handler
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*/
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static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
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struct sk_buff *skb)
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{
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dev_kfree_skb_any(skb);
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return 0;
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}
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/*
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* .event_complete handler
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*/
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static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
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struct sk_buff *skb)
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{
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dev_kfree_skb_any(skb);
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return 0;
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}
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#endif /* _MWIFIEX_SDIO_H */
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