380 lines
9.2 KiB
C
380 lines
9.2 KiB
C
/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/prime_numbers.h>
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#include "../i915_selftest.h"
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#include "i915_random.h"
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static int cpu_set(struct drm_i915_gem_object *obj,
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unsigned long offset,
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u32 v)
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{
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unsigned int needs_clflush;
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struct page *page;
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typeof(v) *map;
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int err;
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err = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
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if (err)
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return err;
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page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
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map = kmap_atomic(page);
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if (needs_clflush & CLFLUSH_BEFORE)
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clflush(map+offset_in_page(offset) / sizeof(*map));
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map[offset_in_page(offset) / sizeof(*map)] = v;
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if (needs_clflush & CLFLUSH_AFTER)
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clflush(map+offset_in_page(offset) / sizeof(*map));
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kunmap_atomic(map);
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i915_gem_obj_finish_shmem_access(obj);
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return 0;
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}
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static int cpu_get(struct drm_i915_gem_object *obj,
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unsigned long offset,
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u32 *v)
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{
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unsigned int needs_clflush;
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struct page *page;
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typeof(v) map;
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int err;
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err = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
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if (err)
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return err;
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page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
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map = kmap_atomic(page);
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if (needs_clflush & CLFLUSH_BEFORE)
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clflush(map+offset_in_page(offset) / sizeof(*map));
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*v = map[offset_in_page(offset) / sizeof(*map)];
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kunmap_atomic(map);
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i915_gem_obj_finish_shmem_access(obj);
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return 0;
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}
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static int gtt_set(struct drm_i915_gem_object *obj,
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unsigned long offset,
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u32 v)
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{
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struct i915_vma *vma;
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typeof(v) *map;
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int err;
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err = i915_gem_object_set_to_gtt_domain(obj, true);
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if (err)
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return err;
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vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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map = i915_vma_pin_iomap(vma);
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i915_vma_unpin(vma);
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if (IS_ERR(map))
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return PTR_ERR(map);
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map[offset / sizeof(*map)] = v;
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i915_vma_unpin_iomap(vma);
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return 0;
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}
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static int gtt_get(struct drm_i915_gem_object *obj,
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unsigned long offset,
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u32 *v)
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{
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struct i915_vma *vma;
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typeof(v) map;
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int err;
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err = i915_gem_object_set_to_gtt_domain(obj, false);
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if (err)
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return err;
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vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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map = i915_vma_pin_iomap(vma);
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i915_vma_unpin(vma);
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if (IS_ERR(map))
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return PTR_ERR(map);
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*v = map[offset / sizeof(*map)];
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i915_vma_unpin_iomap(vma);
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return 0;
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}
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static int wc_set(struct drm_i915_gem_object *obj,
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unsigned long offset,
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u32 v)
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{
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typeof(v) *map;
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int err;
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err = i915_gem_object_set_to_wc_domain(obj, true);
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if (err)
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return err;
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map = i915_gem_object_pin_map(obj, I915_MAP_WC);
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if (IS_ERR(map))
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return PTR_ERR(map);
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map[offset / sizeof(*map)] = v;
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i915_gem_object_unpin_map(obj);
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return 0;
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}
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static int wc_get(struct drm_i915_gem_object *obj,
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unsigned long offset,
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u32 *v)
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{
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typeof(v) map;
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int err;
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err = i915_gem_object_set_to_wc_domain(obj, false);
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if (err)
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return err;
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map = i915_gem_object_pin_map(obj, I915_MAP_WC);
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if (IS_ERR(map))
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return PTR_ERR(map);
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*v = map[offset / sizeof(*map)];
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i915_gem_object_unpin_map(obj);
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return 0;
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}
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static int gpu_set(struct drm_i915_gem_object *obj,
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unsigned long offset,
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u32 v)
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{
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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struct drm_i915_gem_request *rq;
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struct i915_vma *vma;
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u32 *cs;
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int err;
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err = i915_gem_object_set_to_gtt_domain(obj, true);
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if (err)
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return err;
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vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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rq = i915_gem_request_alloc(i915->engine[RCS], i915->kernel_context);
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if (IS_ERR(rq)) {
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i915_vma_unpin(vma);
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return PTR_ERR(rq);
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}
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs)) {
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__i915_add_request(rq, false);
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i915_vma_unpin(vma);
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return PTR_ERR(cs);
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}
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if (INTEL_GEN(i915) >= 8) {
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
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*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
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*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
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*cs++ = v;
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} else if (INTEL_GEN(i915) >= 4) {
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
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*cs++ = 0;
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*cs++ = i915_ggtt_offset(vma) + offset;
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*cs++ = v;
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} else {
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*cs++ = MI_STORE_DWORD_IMM | 1 << 22;
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*cs++ = i915_ggtt_offset(vma) + offset;
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*cs++ = v;
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*cs++ = MI_NOOP;
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}
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intel_ring_advance(rq, cs);
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i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
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i915_vma_unpin(vma);
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reservation_object_lock(obj->resv, NULL);
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reservation_object_add_excl_fence(obj->resv, &rq->fence);
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reservation_object_unlock(obj->resv);
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__i915_add_request(rq, true);
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return 0;
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}
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static bool always_valid(struct drm_i915_private *i915)
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{
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return true;
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}
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static bool needs_mi_store_dword(struct drm_i915_private *i915)
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{
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return intel_engine_can_store_dword(i915->engine[RCS]);
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}
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static const struct igt_coherency_mode {
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const char *name;
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int (*set)(struct drm_i915_gem_object *, unsigned long offset, u32 v);
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int (*get)(struct drm_i915_gem_object *, unsigned long offset, u32 *v);
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bool (*valid)(struct drm_i915_private *i915);
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} igt_coherency_mode[] = {
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{ "cpu", cpu_set, cpu_get, always_valid },
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{ "gtt", gtt_set, gtt_get, always_valid },
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{ "wc", wc_set, wc_get, always_valid },
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{ "gpu", gpu_set, NULL, needs_mi_store_dword },
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{ },
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};
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static int igt_gem_coherency(void *arg)
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{
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const unsigned int ncachelines = PAGE_SIZE/64;
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I915_RND_STATE(prng);
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struct drm_i915_private *i915 = arg;
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const struct igt_coherency_mode *read, *write, *over;
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struct drm_i915_gem_object *obj;
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unsigned long count, n;
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u32 *offsets, *values;
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int err = 0;
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/* We repeatedly write, overwrite and read from a sequence of
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* cachelines in order to try and detect incoherency (unflushed writes
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* from either the CPU or GPU). Each setter/getter uses our cache
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* domain API which should prevent incoherency.
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*/
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offsets = kmalloc_array(ncachelines, 2*sizeof(u32), GFP_KERNEL);
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if (!offsets)
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return -ENOMEM;
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for (count = 0; count < ncachelines; count++)
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offsets[count] = count * 64 + 4 * (count % 16);
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values = offsets + ncachelines;
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mutex_lock(&i915->drm.struct_mutex);
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for (over = igt_coherency_mode; over->name; over++) {
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if (!over->set)
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continue;
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if (!over->valid(i915))
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continue;
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for (write = igt_coherency_mode; write->name; write++) {
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if (!write->set)
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continue;
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if (!write->valid(i915))
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continue;
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for (read = igt_coherency_mode; read->name; read++) {
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if (!read->get)
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continue;
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if (!read->valid(i915))
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continue;
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for_each_prime_number_from(count, 1, ncachelines) {
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obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(obj)) {
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err = PTR_ERR(obj);
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goto unlock;
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}
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i915_random_reorder(offsets, ncachelines, &prng);
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for (n = 0; n < count; n++)
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values[n] = prandom_u32_state(&prng);
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for (n = 0; n < count; n++) {
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err = over->set(obj, offsets[n], ~values[n]);
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if (err) {
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pr_err("Failed to set stale value[%ld/%ld] in object using %s, err=%d\n",
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n, count, over->name, err);
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goto put_object;
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}
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}
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for (n = 0; n < count; n++) {
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err = write->set(obj, offsets[n], values[n]);
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if (err) {
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pr_err("Failed to set value[%ld/%ld] in object using %s, err=%d\n",
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n, count, write->name, err);
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goto put_object;
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}
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}
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for (n = 0; n < count; n++) {
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u32 found;
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err = read->get(obj, offsets[n], &found);
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if (err) {
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pr_err("Failed to get value[%ld/%ld] in object using %s, err=%d\n",
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n, count, read->name, err);
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goto put_object;
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}
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if (found != values[n]) {
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pr_err("Value[%ld/%ld] mismatch, (overwrite with %s) wrote [%s] %x read [%s] %x (inverse %x), at offset %x\n",
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n, count, over->name,
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write->name, values[n],
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read->name, found,
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~values[n], offsets[n]);
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err = -EINVAL;
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goto put_object;
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}
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}
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__i915_gem_object_release_unless_active(obj);
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}
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}
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}
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}
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unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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kfree(offsets);
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return err;
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put_object:
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__i915_gem_object_release_unless_active(obj);
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goto unlock;
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}
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int i915_gem_coherency_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(igt_gem_coherency),
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};
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return i915_subtests(tests, i915);
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}
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