268 lines
8.0 KiB
C
268 lines
8.0 KiB
C
/*
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* Synopsys DesignWare Multimedia Card Interface driver
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* (Based on NXP driver for lpc 31xx)
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*
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* Copyright (C) 2009 NXP Semiconductors
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef LINUX_MMC_DW_MMC_H
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#define LINUX_MMC_DW_MMC_H
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#include <linux/scatterlist.h>
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#include <linux/mmc/core.h>
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#include <linux/dmaengine.h>
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#define MAX_MCI_SLOTS 2
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enum dw_mci_state {
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STATE_IDLE = 0,
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STATE_SENDING_CMD,
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STATE_SENDING_DATA,
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STATE_DATA_BUSY,
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STATE_SENDING_STOP,
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STATE_DATA_ERROR,
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STATE_SENDING_CMD11,
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STATE_WAITING_CMD11_DONE,
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};
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enum {
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EVENT_CMD_COMPLETE = 0,
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EVENT_XFER_COMPLETE,
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EVENT_DATA_COMPLETE,
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EVENT_DATA_ERROR,
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EVENT_XFER_ERROR
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};
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struct mmc_data;
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enum {
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TRANS_MODE_PIO = 0,
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TRANS_MODE_IDMAC,
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TRANS_MODE_EDMAC
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};
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struct dw_mci_dma_slave {
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struct dma_chan *ch;
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enum dma_transfer_direction direction;
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};
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/**
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* struct dw_mci - MMC controller state shared between all slots
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* @lock: Spinlock protecting the queue and associated data.
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* @regs: Pointer to MMIO registers.
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* @fifo_reg: Pointer to MMIO registers for data FIFO
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* @sg: Scatterlist entry currently being processed by PIO code, if any.
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* @sg_miter: PIO mapping scatterlist iterator.
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* @cur_slot: The slot which is currently using the controller.
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* @mrq: The request currently being processed on @cur_slot,
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* or NULL if the controller is idle.
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* @cmd: The command currently being sent to the card, or NULL.
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* @data: The data currently being transferred, or NULL if no data
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* transfer is in progress.
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* @use_dma: Whether DMA channel is initialized or not.
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* @using_dma: Whether DMA is in use for the current transfer.
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* @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
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* @sg_dma: Bus address of DMA buffer.
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* @sg_cpu: Virtual address of DMA buffer.
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* @dma_ops: Pointer to platform-specific DMA callbacks.
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* @cmd_status: Snapshot of SR taken upon completion of the current
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* command. Only valid when EVENT_CMD_COMPLETE is pending.
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* @data_status: Snapshot of SR taken upon completion of the current
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* data transfer. Only valid when EVENT_DATA_COMPLETE or
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* EVENT_DATA_ERROR is pending.
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* @stop_cmdr: Value to be loaded into CMDR when the stop command is
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* to be sent.
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* @dir_status: Direction of current transfer.
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* @tasklet: Tasklet running the request state machine.
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* @card_tasklet: Tasklet handling card detect.
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* @pending_events: Bitmask of events flagged by the interrupt handler
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* to be processed by the tasklet.
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* @completed_events: Bitmask of events which the state machine has
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* processed.
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* @state: Tasklet state.
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* @queue: List of slots waiting for access to the controller.
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* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
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* rate and timeout calculations.
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* @current_speed: Configured rate of the controller.
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* @num_slots: Number of slots available.
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* @verid: Denote Version ID.
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* @dev: Device associated with the MMC controller.
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* @pdata: Platform data associated with the MMC controller.
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* @drv_data: Driver specific data for identified variant of the controller
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* @priv: Implementation defined private data.
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* @biu_clk: Pointer to bus interface unit clock instance.
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* @ciu_clk: Pointer to card interface unit clock instance.
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* @slot: Slots sharing this MMC controller.
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* @fifo_depth: depth of FIFO.
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* @data_shift: log2 of FIFO item size.
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* @part_buf_start: Start index in part_buf.
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* @part_buf_count: Bytes of partial data in part_buf.
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* @part_buf: Simple buffer for partial fifo reads/writes.
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* @push_data: Pointer to FIFO push function.
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* @pull_data: Pointer to FIFO pull function.
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* @quirks: Set of quirks that apply to specific versions of the IP.
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* @irq_flags: The flags to be passed to request_irq.
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* @irq: The irq value to be passed to request_irq.
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* @sdio_id0: Number of slot0 in the SDIO interrupt registers.
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* @dto_timer: Timer for broken data transfer over scheme.
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*
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* Locking
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* =======
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*
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* @lock is a softirq-safe spinlock protecting @queue as well as
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* @cur_slot, @mrq and @state. These must always be updated
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* at the same time while holding @lock.
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*
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* @irq_lock is an irq-safe spinlock protecting the INTMASK register
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* to allow the interrupt handler to modify it directly. Held for only long
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* enough to read-modify-write INTMASK and no other locks are grabbed when
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* holding this one.
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*
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* The @mrq field of struct dw_mci_slot is also protected by @lock,
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* and must always be written at the same time as the slot is added to
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* @queue.
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*
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* @pending_events and @completed_events are accessed using atomic bit
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* operations, so they don't need any locking.
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*
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* None of the fields touched by the interrupt handler need any
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* locking. However, ordering is important: Before EVENT_DATA_ERROR or
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* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
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* interrupts must be disabled and @data_status updated with a
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* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
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* CMDRDY interrupt must be disabled and @cmd_status updated with a
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* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
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* bytes_xfered field of @data must be written. This is ensured by
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* using barriers.
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*/
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struct dw_mci {
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spinlock_t lock;
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spinlock_t irq_lock;
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void __iomem *regs;
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void __iomem *fifo_reg;
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struct scatterlist *sg;
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struct sg_mapping_iter sg_miter;
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struct dw_mci_slot *cur_slot;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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struct mmc_command stop_abort;
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unsigned int prev_blksz;
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unsigned char timing;
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/* DMA interface members*/
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int use_dma;
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int using_dma;
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int dma_64bit_address;
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dma_addr_t sg_dma;
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void *sg_cpu;
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const struct dw_mci_dma_ops *dma_ops;
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/* For idmac */
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unsigned int ring_size;
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/* For edmac */
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struct dw_mci_dma_slave *dms;
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/* Registers's physical base address */
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resource_size_t phy_regs;
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u32 cmd_status;
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u32 data_status;
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u32 stop_cmdr;
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u32 dir_status;
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struct tasklet_struct tasklet;
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unsigned long pending_events;
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unsigned long completed_events;
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enum dw_mci_state state;
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struct list_head queue;
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u32 bus_hz;
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u32 current_speed;
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u32 num_slots;
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u32 fifoth_val;
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u16 verid;
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struct device *dev;
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struct dw_mci_board *pdata;
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const struct dw_mci_drv_data *drv_data;
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void *priv;
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struct clk *biu_clk;
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struct clk *ciu_clk;
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struct dw_mci_slot *slot[MAX_MCI_SLOTS];
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/* FIFO push and pull */
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int fifo_depth;
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int data_shift;
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u8 part_buf_start;
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u8 part_buf_count;
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union {
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u16 part_buf16;
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u32 part_buf32;
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u64 part_buf;
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};
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void (*push_data)(struct dw_mci *host, void *buf, int cnt);
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void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
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/* Workaround flags */
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u32 quirks;
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bool vqmmc_enabled;
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unsigned long irq_flags; /* IRQ flags */
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int irq;
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int sdio_id0;
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struct timer_list cmd11_timer;
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struct timer_list dto_timer;
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};
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/* DMA ops for Internal/External DMAC interface */
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struct dw_mci_dma_ops {
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/* DMA Ops */
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int (*init)(struct dw_mci *host);
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int (*start)(struct dw_mci *host, unsigned int sg_len);
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void (*complete)(void *host);
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void (*stop)(struct dw_mci *host);
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void (*cleanup)(struct dw_mci *host);
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void (*exit)(struct dw_mci *host);
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};
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/* IP Quirks/flags. */
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/* Timer for broken data transfer over scheme */
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#define DW_MCI_QUIRK_BROKEN_DTO BIT(0)
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struct dma_pdata;
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/* Board platform data */
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struct dw_mci_board {
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u32 num_slots;
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u32 quirks; /* Workaround / Quirk flags */
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unsigned int bus_hz; /* Clock speed at the cclk_in pad */
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u32 caps; /* Capabilities */
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u32 caps2; /* More capabilities */
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u32 pm_caps; /* PM capabilities */
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/*
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* Override fifo depth. If 0, autodetect it from the FIFOTH register,
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* but note that this may not be reliable after a bootloader has used
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* it.
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*/
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unsigned int fifo_depth;
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/* delay in mS before detecting cards after interrupt */
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u32 detect_delay_ms;
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struct dw_mci_dma_ops *dma_ops;
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struct dma_pdata *data;
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};
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#endif /* LINUX_MMC_DW_MMC_H */
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