Maxime Chevallier fef2998203 net: altera: tse: convert to phylink ... Convert the Altera Triple Speed Ethernet Controller to phylink. This controller supports MII, GMII and RGMII with its MAC, and SGMII + 1000BaseX through a small embedded PCS. The PCS itself has a register set very similar to what is found in a typical 802.3 ethernet PHY, but this register set memory-mapped instead of lying on an mdio bus. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2022-09-05 10:16:53 +01:00
..
Kconfig	net: altera: tse: convert to phylink	2022-09-05 10:16:53 +01:00
Makefile	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
altera_msgdma.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
altera_msgdma.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
altera_msgdmahw.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
altera_sgdma.c	net: ethernet: altera: cleanup comments	2022-02-16 20:33:04 -08:00
altera_sgdma.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
altera_sgdmahw.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
altera_tse.h	net: altera: tse: convert to phylink	2022-09-05 10:16:53 +01:00
altera_tse_ethtool.c	net: altera: tse: convert to phylink	2022-09-05 10:16:53 +01:00
altera_tse_main.c	net: altera: tse: convert to phylink	2022-09-05 10:16:53 +01:00
altera_utils.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
altera_utils.h	net: altera: Replace kernel.h with the necessary inclusions	2022-06-07 11:13:43 +02:00