786 lines
27 KiB
C
786 lines
27 KiB
C
#ifndef ADRENO_PM4_XML
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#define ADRENO_PM4_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
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Copyright (C) 2013-2016 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum vgt_event_type {
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VS_DEALLOC = 0,
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PS_DEALLOC = 1,
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VS_DONE_TS = 2,
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PS_DONE_TS = 3,
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CACHE_FLUSH_TS = 4,
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CONTEXT_DONE = 5,
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CACHE_FLUSH = 6,
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HLSQ_FLUSH = 7,
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VIZQUERY_START = 7,
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VIZQUERY_END = 8,
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SC_WAIT_WC = 9,
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RST_PIX_CNT = 13,
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RST_VTX_CNT = 14,
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TILE_FLUSH = 15,
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STAT_EVENT = 16,
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CACHE_FLUSH_AND_INV_TS_EVENT = 20,
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ZPASS_DONE = 21,
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CACHE_FLUSH_AND_INV_EVENT = 22,
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PERFCOUNTER_START = 23,
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PERFCOUNTER_STOP = 24,
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VS_FETCH_DONE = 27,
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FACENESS_FLUSH = 28,
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UNK_1C = 28,
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UNK_1D = 29,
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BLIT = 30,
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UNK_26 = 38,
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};
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enum pc_di_primtype {
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DI_PT_NONE = 0,
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DI_PT_POINTLIST_PSIZE = 1,
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DI_PT_LINELIST = 2,
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DI_PT_LINESTRIP = 3,
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DI_PT_TRILIST = 4,
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DI_PT_TRIFAN = 5,
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DI_PT_TRISTRIP = 6,
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DI_PT_LINELOOP = 7,
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DI_PT_RECTLIST = 8,
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DI_PT_POINTLIST = 9,
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DI_PT_LINE_ADJ = 10,
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DI_PT_LINESTRIP_ADJ = 11,
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DI_PT_TRI_ADJ = 12,
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DI_PT_TRISTRIP_ADJ = 13,
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};
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enum pc_di_src_sel {
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DI_SRC_SEL_DMA = 0,
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DI_SRC_SEL_IMMEDIATE = 1,
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DI_SRC_SEL_AUTO_INDEX = 2,
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DI_SRC_SEL_RESERVED = 3,
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};
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enum pc_di_index_size {
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INDEX_SIZE_IGN = 0,
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INDEX_SIZE_16_BIT = 0,
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INDEX_SIZE_32_BIT = 1,
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INDEX_SIZE_8_BIT = 2,
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INDEX_SIZE_INVALID = 0,
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};
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enum pc_di_vis_cull_mode {
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IGNORE_VISIBILITY = 0,
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USE_VISIBILITY = 1,
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};
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enum adreno_pm4_packet_type {
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CP_TYPE0_PKT = 0,
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CP_TYPE1_PKT = 0x40000000,
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CP_TYPE2_PKT = 0x80000000,
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CP_TYPE3_PKT = 0xc0000000,
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CP_TYPE4_PKT = 0x40000000,
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CP_TYPE7_PKT = 0x70000000,
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};
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enum adreno_pm4_type3_packets {
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CP_ME_INIT = 72,
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CP_NOP = 16,
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CP_PREEMPT_ENABLE = 28,
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CP_PREEMPT_TOKEN = 30,
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CP_INDIRECT_BUFFER = 63,
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CP_INDIRECT_BUFFER_PFD = 55,
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CP_WAIT_FOR_IDLE = 38,
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CP_WAIT_REG_MEM = 60,
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CP_WAIT_REG_EQ = 82,
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CP_WAIT_REG_GTE = 83,
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CP_WAIT_UNTIL_READ = 92,
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CP_WAIT_IB_PFD_COMPLETE = 93,
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CP_REG_RMW = 33,
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CP_SET_BIN_DATA = 47,
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CP_REG_TO_MEM = 62,
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CP_MEM_WRITE = 61,
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CP_MEM_WRITE_CNTR = 79,
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CP_COND_EXEC = 68,
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CP_COND_WRITE = 69,
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CP_EVENT_WRITE = 70,
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CP_EVENT_WRITE_SHD = 88,
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CP_EVENT_WRITE_CFL = 89,
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CP_EVENT_WRITE_ZPD = 91,
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CP_RUN_OPENCL = 49,
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CP_DRAW_INDX = 34,
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CP_DRAW_INDX_2 = 54,
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CP_DRAW_INDX_BIN = 52,
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CP_DRAW_INDX_2_BIN = 53,
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CP_VIZ_QUERY = 35,
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CP_SET_STATE = 37,
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CP_SET_CONSTANT = 45,
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CP_IM_LOAD = 39,
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CP_IM_LOAD_IMMEDIATE = 43,
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CP_LOAD_CONSTANT_CONTEXT = 46,
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CP_INVALIDATE_STATE = 59,
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CP_SET_SHADER_BASES = 74,
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CP_SET_BIN_MASK = 80,
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CP_SET_BIN_SELECT = 81,
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CP_CONTEXT_UPDATE = 94,
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CP_INTERRUPT = 64,
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CP_IM_STORE = 44,
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CP_SET_DRAW_INIT_FLAGS = 75,
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CP_SET_PROTECTED_MODE = 95,
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CP_BOOTSTRAP_UCODE = 111,
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CP_LOAD_STATE = 48,
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CP_COND_INDIRECT_BUFFER_PFE = 58,
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CP_COND_INDIRECT_BUFFER_PFD = 50,
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CP_INDIRECT_BUFFER_PFE = 63,
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CP_SET_BIN = 76,
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CP_TEST_TWO_MEMS = 113,
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CP_REG_WR_NO_CTXT = 120,
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CP_RECORD_PFP_TIMESTAMP = 17,
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CP_SET_SECURE_MODE = 102,
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CP_WAIT_FOR_ME = 19,
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CP_SET_DRAW_STATE = 67,
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CP_DRAW_INDX_OFFSET = 56,
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CP_DRAW_INDIRECT = 40,
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CP_DRAW_INDX_INDIRECT = 41,
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CP_DRAW_AUTO = 36,
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CP_UNKNOWN_19 = 25,
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CP_UNKNOWN_1A = 26,
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CP_UNKNOWN_4E = 78,
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CP_WIDE_REG_WRITE = 116,
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CP_SCRATCH_TO_REG = 77,
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CP_REG_TO_SCRATCH = 74,
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CP_WAIT_MEM_WRITES = 18,
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CP_COND_REG_EXEC = 71,
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CP_MEM_TO_REG = 66,
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CP_EXEC_CS = 51,
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CP_PERFCOUNTER_ACTION = 80,
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CP_SMMU_TABLE_UPDATE = 83,
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CP_CONTEXT_REG_BUNCH = 92,
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CP_YIELD_ENABLE = 28,
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CP_SKIP_IB2_ENABLE_GLOBAL = 29,
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CP_SKIP_IB2_ENABLE_LOCAL = 35,
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CP_SET_SUBDRAW_SIZE = 53,
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CP_SET_VISIBILITY_OVERRIDE = 100,
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CP_PREEMPT_ENABLE_GLOBAL = 105,
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CP_PREEMPT_ENABLE_LOCAL = 106,
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CP_CONTEXT_SWITCH_YIELD = 107,
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CP_SET_RENDER_MODE = 108,
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CP_COMPUTE_CHECKPOINT = 110,
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CP_MEM_TO_MEM = 115,
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CP_BLIT = 44,
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IN_IB_PREFETCH_END = 23,
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IN_SUBBLK_PREFETCH = 31,
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IN_INSTR_PREFETCH = 32,
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IN_INSTR_MATCH = 71,
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IN_CONST_PREFETCH = 73,
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IN_INCR_UPDT_STATE = 85,
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IN_INCR_UPDT_CONST = 86,
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IN_INCR_UPDT_INSTR = 87,
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};
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enum adreno_state_block {
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SB_VERT_TEX = 0,
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SB_VERT_MIPADDR = 1,
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SB_FRAG_TEX = 2,
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SB_FRAG_MIPADDR = 3,
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SB_VERT_SHADER = 4,
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SB_GEOM_SHADER = 5,
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SB_FRAG_SHADER = 6,
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SB_COMPUTE_SHADER = 7,
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};
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enum adreno_state_type {
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ST_SHADER = 0,
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ST_CONSTANTS = 1,
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};
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enum adreno_state_src {
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SS_DIRECT = 0,
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SS_INVALID_ALL_IC = 2,
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SS_INVALID_PART_IC = 3,
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SS_INDIRECT = 4,
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SS_INDIRECT_TCM = 5,
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SS_INDIRECT_STM = 6,
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};
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enum a4xx_index_size {
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INDEX4_SIZE_8_BIT = 0,
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INDEX4_SIZE_16_BIT = 1,
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INDEX4_SIZE_32_BIT = 2,
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};
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enum render_mode_cmd {
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BYPASS = 1,
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GMEM = 3,
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BLIT2D = 5,
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};
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enum cp_blit_cmd {
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BLIT_OP_FILL = 0,
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BLIT_OP_BLIT = 1,
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};
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#define REG_CP_LOAD_STATE_0 0x00000000
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#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
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#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
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static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
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{
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return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
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}
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#define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
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#define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
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static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
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{
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return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
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}
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#define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
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#define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
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static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
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{
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return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
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}
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#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
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#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
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static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
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{
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return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
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}
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#define REG_CP_LOAD_STATE_1 0x00000001
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#define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
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#define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
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static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
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{
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return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
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}
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#define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
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#define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
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static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
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{
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return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
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}
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#define REG_CP_LOAD_STATE_2 0x00000002
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#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
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#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0
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static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)
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{
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return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK;
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}
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#define REG_CP_DRAW_INDX_0 0x00000000
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#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
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#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
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}
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#define REG_CP_DRAW_INDX_1 0x00000001
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#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
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#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
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}
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#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
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#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
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static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
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}
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#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
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#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
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static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
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}
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#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
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#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
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static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
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{
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return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
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}
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#define CP_DRAW_INDX_1_NOT_EOP 0x00001000
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#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
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#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
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#define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
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#define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
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static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
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}
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#define REG_CP_DRAW_INDX_2 0x00000002
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#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
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#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
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}
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#define REG_CP_DRAW_INDX_3 0x00000003
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#define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
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#define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
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}
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#define REG_CP_DRAW_INDX_4 0x00000004
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#define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
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#define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
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}
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#define REG_CP_DRAW_INDX_2_0 0x00000000
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#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
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#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
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}
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#define REG_CP_DRAW_INDX_2_1 0x00000001
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#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
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#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
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}
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#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
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#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
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static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
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}
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#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
|
|
#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
|
|
static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
|
|
}
|
|
#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
|
|
#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
|
|
static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
|
|
}
|
|
#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
|
|
#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
|
|
#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
|
|
#define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
|
|
#define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
|
|
static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
|
|
}
|
|
|
|
#define REG_CP_DRAW_INDX_2_2 0x00000002
|
|
#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
|
|
#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
|
|
static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
|
|
}
|
|
|
|
#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
|
|
#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
|
|
#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
|
|
}
|
|
#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
|
|
#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
|
|
}
|
|
#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
|
|
#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
|
|
}
|
|
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
|
|
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
|
|
}
|
|
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
|
|
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
|
|
}
|
|
|
|
#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
|
|
#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
|
|
#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
|
|
}
|
|
|
|
#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
|
|
#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
|
|
#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
|
|
}
|
|
|
|
#define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
|
|
|
|
#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
|
|
#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
|
|
#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
|
|
}
|
|
|
|
#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
|
|
#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
|
|
#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
|
|
static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
|
|
{
|
|
return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
|
|
|
static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
|
#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
|
|
#define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
|
|
static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
|
|
}
|
|
#define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
|
|
#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
|
|
#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
|
|
#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
|
|
#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
|
|
#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
|
|
static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
|
|
#define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
|
|
#define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
|
|
static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
|
|
#define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
|
|
#define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
|
|
static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_BIN_0 0x00000000
|
|
|
|
#define REG_CP_SET_BIN_1 0x00000001
|
|
#define CP_SET_BIN_1_X1__MASK 0x0000ffff
|
|
#define CP_SET_BIN_1_X1__SHIFT 0
|
|
static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
|
|
}
|
|
#define CP_SET_BIN_1_Y1__MASK 0xffff0000
|
|
#define CP_SET_BIN_1_Y1__SHIFT 16
|
|
static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_BIN_2 0x00000002
|
|
#define CP_SET_BIN_2_X2__MASK 0x0000ffff
|
|
#define CP_SET_BIN_2_X2__SHIFT 0
|
|
static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
|
|
}
|
|
#define CP_SET_BIN_2_Y2__MASK 0xffff0000
|
|
#define CP_SET_BIN_2_Y2__SHIFT 16
|
|
static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_BIN_DATA_0 0x00000000
|
|
#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
|
|
#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
|
|
static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_BIN_DATA_1 0x00000001
|
|
#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
|
|
#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
|
|
static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
|
|
}
|
|
|
|
#define REG_CP_REG_TO_MEM_0 0x00000000
|
|
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
|
|
#define CP_REG_TO_MEM_0_REG__SHIFT 0
|
|
static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
|
|
{
|
|
return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
|
|
}
|
|
#define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
|
|
#define CP_REG_TO_MEM_0_CNT__SHIFT 19
|
|
static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
|
|
{
|
|
return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
|
|
}
|
|
#define CP_REG_TO_MEM_0_64B 0x40000000
|
|
#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
|
|
|
|
#define REG_CP_REG_TO_MEM_1 0x00000001
|
|
#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
|
|
#define CP_REG_TO_MEM_1_DEST__SHIFT 0
|
|
static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
|
|
{
|
|
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
|
|
}
|
|
|
|
#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
|
|
|
|
#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
|
|
#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
|
|
#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
|
|
static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
|
|
{
|
|
return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
|
|
}
|
|
|
|
#define REG_CP_DISPATCH_COMPUTE_2 0x00000002
|
|
#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
|
|
#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
|
|
static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
|
|
{
|
|
return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
|
|
}
|
|
|
|
#define REG_CP_DISPATCH_COMPUTE_3 0x00000003
|
|
#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
|
|
#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
|
|
static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
|
|
{
|
|
return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_RENDER_MODE_0 0x00000000
|
|
#define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
|
|
#define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
|
|
static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
|
|
{
|
|
return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_RENDER_MODE_1 0x00000001
|
|
#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
|
|
#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
|
|
static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_RENDER_MODE_2 0x00000002
|
|
#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
|
|
#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
|
|
static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_RENDER_MODE_3 0x00000003
|
|
#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
|
|
|
|
#define REG_CP_SET_RENDER_MODE_4 0x00000004
|
|
|
|
#define REG_CP_SET_RENDER_MODE_5 0x00000005
|
|
#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
|
|
#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
|
|
static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_RENDER_MODE_6 0x00000006
|
|
#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
|
|
#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
|
|
static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
|
|
}
|
|
|
|
#define REG_CP_SET_RENDER_MODE_7 0x00000007
|
|
#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
|
|
#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
|
|
static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
|
|
{
|
|
return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
|
|
}
|
|
|
|
#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
|
|
|
|
#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
|
|
#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
|
|
#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
|
|
static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
|
|
{
|
|
return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
|
|
}
|
|
|
|
#define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
|
|
#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
|
|
#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
|
|
static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
|
|
{
|
|
return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
|
|
}
|
|
|
|
#define REG_CP_EVENT_WRITE_0 0x00000000
|
|
#define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
|
|
#define CP_EVENT_WRITE_0_EVENT__SHIFT 0
|
|
static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
|
|
{
|
|
return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
|
|
}
|
|
|
|
#define REG_CP_EVENT_WRITE_1 0x00000001
|
|
#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
|
|
#define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
|
|
static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
|
|
{
|
|
return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
|
|
}
|
|
|
|
#define REG_CP_EVENT_WRITE_2 0x00000002
|
|
#define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
|
|
#define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
|
|
static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
|
|
{
|
|
return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
|
|
}
|
|
|
|
#define REG_CP_EVENT_WRITE_3 0x00000003
|
|
|
|
#define REG_CP_BLIT_0 0x00000000
|
|
#define CP_BLIT_0_OP__MASK 0x0000000f
|
|
#define CP_BLIT_0_OP__SHIFT 0
|
|
static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
|
|
{
|
|
return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
|
|
}
|
|
|
|
#define REG_CP_BLIT_1 0x00000001
|
|
#define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
|
|
#define CP_BLIT_1_SRC_X1__SHIFT 0
|
|
static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
|
|
{
|
|
return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
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}
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#define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
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#define CP_BLIT_1_SRC_Y1__SHIFT 16
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static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
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{
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return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
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}
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|
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#define REG_CP_BLIT_2 0x00000002
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#define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
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#define CP_BLIT_2_SRC_X2__SHIFT 0
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static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
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|
{
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|
return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
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|
}
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|
#define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
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#define CP_BLIT_2_SRC_Y2__SHIFT 16
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static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
|
|
{
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|
return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
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|
}
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|
|
|
#define REG_CP_BLIT_3 0x00000003
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#define CP_BLIT_3_DST_X1__MASK 0x0000ffff
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#define CP_BLIT_3_DST_X1__SHIFT 0
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|
static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
|
|
{
|
|
return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
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|
}
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#define CP_BLIT_3_DST_Y1__MASK 0xffff0000
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|
#define CP_BLIT_3_DST_Y1__SHIFT 16
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|
static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
|
|
{
|
|
return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
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|
}
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|
|
|
#define REG_CP_BLIT_4 0x00000004
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|
#define CP_BLIT_4_DST_X2__MASK 0x0000ffff
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|
#define CP_BLIT_4_DST_X2__SHIFT 0
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|
static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
|
|
{
|
|
return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
|
|
}
|
|
#define CP_BLIT_4_DST_Y2__MASK 0xffff0000
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|
#define CP_BLIT_4_DST_Y2__SHIFT 16
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|
static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
|
|
{
|
|
return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
|
|
}
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|
|
|
|
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#endif /* ADRENO_PM4_XML */
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