157 lines
4.5 KiB
C
157 lines
4.5 KiB
C
/*
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* Geode GX display controller.
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*
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* Copyright (C) 2005 Arcom Control Systems Ltd.
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*
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* Portions from AMD's original 2.4 driver:
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* Copyright (C) 2004 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by * the
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* Free Software Foundation; either version 2 of the License, or * (at your
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* option) any later version.
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*/
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#include <linux/spinlock.h>
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#include <linux/fb.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/div64.h>
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#include <asm/delay.h>
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#include "geodefb.h"
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#include "display_gx.h"
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int gx_frame_buffer_size(void)
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{
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/* Assuming 16 MiB. */
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return 16*1024*1024;
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}
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int gx_line_delta(int xres, int bpp)
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{
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/* Must be a multiple of 8 bytes. */
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return (xres * (bpp >> 3) + 7) & ~0x7;
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}
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static void gx_set_mode(struct fb_info *info)
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{
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struct geodefb_par *par = info->par;
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u32 gcfg, dcfg;
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int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
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int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
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/* Unlock the display controller registers. */
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readl(par->dc_regs + DC_UNLOCK);
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writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
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gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
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dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);
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/* Disable the timing generator. */
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dcfg &= ~(DC_DCFG_TGEN);
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writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
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/* Wait for pending memory requests before disabling the FIFO load. */
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udelay(100);
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/* Disable FIFO load and compression. */
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gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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/* Setup DCLK and its divisor. */
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par->vid_ops->set_dclk(info);
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/*
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* Setup new mode.
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*/
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/* Clear all unused feature bits. */
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gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
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dcfg = 0;
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/* Set FIFO priority (default 6/5) and enable. */
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/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
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gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
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/* Framebuffer start offset. */
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writel(0, par->dc_regs + DC_FB_ST_OFFSET);
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/* Line delta and line buffer length. */
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writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
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writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
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par->dc_regs + DC_LINE_SIZE);
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/* Enable graphics and video data and unmask address lines. */
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dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
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/* Set pixel format. */
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switch (info->var.bits_per_pixel) {
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case 8:
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dcfg |= DC_DCFG_DISP_MODE_8BPP;
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break;
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case 16:
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dcfg |= DC_DCFG_DISP_MODE_16BPP;
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dcfg |= DC_DCFG_16BPP_MODE_565;
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break;
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case 32:
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dcfg |= DC_DCFG_DISP_MODE_24BPP;
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dcfg |= DC_DCFG_PALB;
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break;
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}
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/* Enable timing generator. */
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dcfg |= DC_DCFG_TGEN;
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/* Horizontal and vertical timings. */
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hactive = info->var.xres;
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hblankstart = hactive;
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hsyncstart = hblankstart + info->var.right_margin;
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hsyncend = hsyncstart + info->var.hsync_len;
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hblankend = hsyncend + info->var.left_margin;
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htotal = hblankend;
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vactive = info->var.yres;
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vblankstart = vactive;
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vsyncstart = vblankstart + info->var.lower_margin;
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vsyncend = vsyncstart + info->var.vsync_len;
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vblankend = vsyncend + info->var.upper_margin;
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vtotal = vblankend;
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writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
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writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
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writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
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writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
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writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
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writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
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/* Write final register values. */
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writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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par->vid_ops->configure_display(info);
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/* Relock display controller registers */
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writel(0, par->dc_regs + DC_UNLOCK);
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}
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static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
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unsigned red, unsigned green, unsigned blue)
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{
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struct geodefb_par *par = info->par;
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int val;
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/* Hardware palette is in RGB 8-8-8 format. */
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val = (red << 8) & 0xff0000;
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val |= (green) & 0x00ff00;
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val |= (blue >> 8) & 0x0000ff;
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writel(regno, par->dc_regs + DC_PAL_ADDRESS);
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writel(val, par->dc_regs + DC_PAL_DATA);
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}
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struct geode_dc_ops gx_dc_ops = {
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.set_mode = gx_set_mode,
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.set_palette_reg = gx_set_hw_palette_reg,
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};
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