187 lines
4.0 KiB
C
187 lines
4.0 KiB
C
/* Copyright (c) 2014 Linaro Ltd.
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* Copyright (c) 2014 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/of_mdio.h>
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#include <linux/delay.h>
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#define MDIO_CMD_REG 0x0
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#define MDIO_ADDR_REG 0x4
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#define MDIO_WDATA_REG 0x8
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#define MDIO_RDATA_REG 0xc
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#define MDIO_STA_REG 0x10
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#define MDIO_START BIT(14)
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#define MDIO_R_VALID BIT(1)
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#define MDIO_READ (BIT(12) | BIT(11) | MDIO_START)
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#define MDIO_WRITE (BIT(12) | BIT(10) | MDIO_START)
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struct hip04_mdio_priv {
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void __iomem *base;
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};
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#define WAIT_TIMEOUT 10
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static int hip04_mdio_wait_ready(struct mii_bus *bus)
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{
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struct hip04_mdio_priv *priv = bus->priv;
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int i;
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for (i = 0; readl_relaxed(priv->base + MDIO_CMD_REG) & MDIO_START; i++) {
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if (i == WAIT_TIMEOUT)
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return -ETIMEDOUT;
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msleep(20);
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}
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return 0;
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}
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static int hip04_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct hip04_mdio_priv *priv = bus->priv;
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u32 val;
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int ret;
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ret = hip04_mdio_wait_ready(bus);
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if (ret < 0)
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goto out;
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val = regnum | (mii_id << 5) | MDIO_READ;
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writel_relaxed(val, priv->base + MDIO_CMD_REG);
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ret = hip04_mdio_wait_ready(bus);
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if (ret < 0)
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goto out;
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val = readl_relaxed(priv->base + MDIO_STA_REG);
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if (val & MDIO_R_VALID) {
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dev_err(bus->parent, "SMI bus read not valid\n");
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ret = -ENODEV;
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goto out;
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}
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val = readl_relaxed(priv->base + MDIO_RDATA_REG);
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ret = val & 0xFFFF;
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out:
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return ret;
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}
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static int hip04_mdio_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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struct hip04_mdio_priv *priv = bus->priv;
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u32 val;
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int ret;
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ret = hip04_mdio_wait_ready(bus);
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if (ret < 0)
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goto out;
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writel_relaxed(value, priv->base + MDIO_WDATA_REG);
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val = regnum | (mii_id << 5) | MDIO_WRITE;
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writel_relaxed(val, priv->base + MDIO_CMD_REG);
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out:
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return ret;
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}
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static int hip04_mdio_reset(struct mii_bus *bus)
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{
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int temp, i;
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for (i = 0; i < PHY_MAX_ADDR; i++) {
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hip04_mdio_write(bus, i, 22, 0);
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temp = hip04_mdio_read(bus, i, MII_BMCR);
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if (temp < 0)
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continue;
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temp |= BMCR_RESET;
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if (hip04_mdio_write(bus, i, MII_BMCR, temp) < 0)
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continue;
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}
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mdelay(500);
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return 0;
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}
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static int hip04_mdio_probe(struct platform_device *pdev)
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{
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struct resource *r;
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struct mii_bus *bus;
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struct hip04_mdio_priv *priv;
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int ret;
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bus = mdiobus_alloc_size(sizeof(struct hip04_mdio_priv));
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if (!bus) {
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dev_err(&pdev->dev, "Cannot allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->name = "hip04_mdio_bus";
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bus->read = hip04_mdio_read;
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bus->write = hip04_mdio_write;
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bus->reset = hip04_mdio_reset;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
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bus->parent = &pdev->dev;
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priv = bus->priv;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(priv->base)) {
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ret = PTR_ERR(priv->base);
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goto out_mdio;
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}
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ret = of_mdiobus_register(bus, pdev->dev.of_node);
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if (ret < 0) {
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dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
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goto out_mdio;
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}
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platform_set_drvdata(pdev, bus);
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return 0;
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out_mdio:
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mdiobus_free(bus);
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return ret;
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}
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static int hip04_mdio_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = platform_get_drvdata(pdev);
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mdiobus_unregister(bus);
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mdiobus_free(bus);
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return 0;
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}
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static const struct of_device_id hip04_mdio_match[] = {
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{ .compatible = "hisilicon,hip04-mdio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hip04_mdio_match);
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static struct platform_driver hip04_mdio_driver = {
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.probe = hip04_mdio_probe,
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.remove = hip04_mdio_remove,
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.driver = {
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.name = "hip04-mdio",
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.owner = THIS_MODULE,
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.of_match_table = hip04_mdio_match,
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},
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};
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module_platform_driver(hip04_mdio_driver);
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MODULE_DESCRIPTION("HISILICON P04 MDIO interface driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:hip04-mdio");
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