150 lines
5.8 KiB
C
150 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
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#define __SOC_MEDIATEK_MT8188_MMSYS_H
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#define MT8188_VDO0_OVL_MOUT_EN 0xf14
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#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
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#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
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#define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
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#define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
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#define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
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#define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
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#define MT8188_VDO0_SEL_IN 0xf34
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#define MT8188_VDO0_SEL_OUT 0xf38
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#define MT8188_VDO0_DISP_RDMA_SEL 0xf40
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#define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0)
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#define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0)
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#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0)
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#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0)
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#define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK GENMASK(8, 8)
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#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 (0 << 8)
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#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0 (1 << 8)
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#define MT8188_VDO0_DSI0_SEL_IN 0xf44
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#define MT8188_SEL_IN_DSI0_FROM_MASK BIT(0)
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#define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 0)
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#define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 0)
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#define MT8188_VDO0_DP_INTF0_SEL_IN 0xf4C
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#define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0)
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#define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT (0 << 0)
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#define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 0)
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#define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 (3 << 0)
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#define MT8188_VDO0_DISP_DITHER0_SEL_OUT 0xf58
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#define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0)
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#define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
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#define MT8188_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
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#define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 (6 << 0)
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#define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 (7 << 0)
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#define MT8188_VDO0_VPP_MERGE_SEL 0xf60
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#define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
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#define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
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#define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT (3 << 0)
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#define MT8188_SOUT_VPP_MERGE_TO_MASK GENMASK(6, 4)
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#define MT8188_SOUT_VPP_MERGE_TO_DSI1 (0 << 4)
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#define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 4)
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#define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 4)
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#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 4)
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#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 4)
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#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 (5 << 4)
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#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
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#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
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#define MT8188_VDO0_DSC_WARP_SEL 0xf64
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#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0)
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#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 (0 << 0)
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#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE (1 << 0)
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#define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(19, 16)
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#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 BIT(16)
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#define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(17)
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#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18)
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#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19)
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static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
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MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
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MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
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MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
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MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
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MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
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MT8188_VDO0_DSC_WARP_SEL,
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MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
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MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
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MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
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MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
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MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK,
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MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DISP_DITHER0_SEL_OUT,
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MT8188_SOUT_DISP_DITHER0_TO_MASK,
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MT8188_SOUT_DISP_DITHER0_TO_DSI0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
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MT8188_VDO0_DISP_DITHER0_SEL_OUT,
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MT8188_SOUT_DISP_DITHER0_TO_MASK,
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MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DP_INTF0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
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MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
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MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
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MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
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},
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};
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#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
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