64b37b2a63
The driver call nand_scan_ident in 8 bit mode, then readid or onfi detection are done (and detect bus width). The driver should update its bus width before calling nand_scan_tail. This work because readid and onfi are read work 8 byte mode. Note that nand_scan_ident send command (NAND_CMD_RESET, NAND_CMD_READID, NAND_CMD_PARAM), address and read data The ONFI specificication is not very clear for x16 device if high byte of address should be driven to 0, but according to [1] it should be ok to not drive it during autodetection. [1] 3.3.2. Target Initialization [...] The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page. Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> |
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| .. | ||
| bbm.h | ||
| blktrans.h | ||
| cfi.h | ||
| cfi_endian.h | ||
| concat.h | ||
| doc2000.h | ||
| flashchip.h | ||
| fsmc.h | ||
| ftl.h | ||
| gen_probe.h | ||
| inftl.h | ||
| latch-addr-flash.h | ||
| lpc32xx_mlc.h | ||
| lpc32xx_slc.h | ||
| map.h | ||
| mtd.h | ||
| mtdram.h | ||
| nand-gpio.h | ||
| nand.h | ||
| nand_bch.h | ||
| nand_ecc.h | ||
| ndfc.h | ||
| nftl.h | ||
| onenand.h | ||
| onenand_regs.h | ||
| partitions.h | ||
| pfow.h | ||
| physmap.h | ||
| pismo.h | ||
| plat-ram.h | ||
| qinfo.h | ||
| sh_flctl.h | ||
| sharpsl.h | ||
| spear_smi.h | ||
| super.h | ||
| ubi.h | ||
| xip.h | ||