138 lines
5.8 KiB
C
138 lines
5.8 KiB
C
/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2012 Analog Devices Inc.
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* Licensed under the Clear BSD license.
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*/
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/* This file should be up to date with:
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* - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
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*/
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#if __SILICON_REVISION__ < 0
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# error will not work on BF609 silicon version
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#endif
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
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#define ANOMALY_16000003 (1)
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/* The EPPI Data Enable (DEN) Signal is Not Functional */
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#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
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/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
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#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
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/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
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#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
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/* DDR2 Memory Reads May Fail Intermittently */
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#define ANOMALY_16000007 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_16000008 (1)
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/* TestSET Instruction Cannot Be Interrupted */
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#define ANOMALY_16000009 (1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_16000010 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_16000011 (1)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_16000012 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_16000013 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_16000014 (1)
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_16000015 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_16000017 (1)
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/* RSI Boot Cleanup Routine Does Not Clear Registers */
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#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
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/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
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#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
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/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
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#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
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/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
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#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
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/* Boot Code Fails to Enable Parity Fault Detection */
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#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
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/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
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#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
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/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
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#define ANOMALY_16000024 (1)
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/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
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#define ANOMALY_16000025 (1)
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/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
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#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
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/* Default SPI Master Boot Mode Setting is Incorrect */
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#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
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/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
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#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
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/* Interrupted Core Reads of MMRs May Cause Data Loss */
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#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
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/* Incorrect Default USB_PLL_OSC.PLLM Value */
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#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
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/* Core Reads of System MMRs May Cause the Core to Hang */
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#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
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/* PPI Data Underflow on First Word Not Reported in Certain Modes */
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#define ANOMALY_16000033 (1)
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/* CNV1 Red Pixel Substitution feature not functional in the PVP */
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#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
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/* IPF0 Output Port Color Separation feature not functional */
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#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
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/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
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#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
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/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
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#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
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/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
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#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
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/* CGU_STAT.PLOCKERR Bit May be Unreliable */
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#define ANOMALY_16000039 (1)
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/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
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#define ANOMALY_16000040 (1)
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/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
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#define ANOMALY_16000041 (1)
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/* Instruction Cache Failure When Parity Is Enabled */
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#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000189 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000278 (0)
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#define ANOMALY_05000281 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000312 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000450 (0)
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#define ANOMALY_05000456 (0)
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#define ANOMALY_05000480 (0)
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#define ANOMALY_05000481 (1)
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/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
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#define ANOMALY_05000491 ANOMALY_16000008
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#define ANOMALY_05000477 ANOMALY_16000009
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#define ANOMALY_05000443 ANOMALY_16000010
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#define ANOMALY_05000461 ANOMALY_16000011
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#define ANOMALY_05000426 ANOMALY_16000012
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#define ANOMALY_05000310 ANOMALY_16000013
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#define ANOMALY_05000245 ANOMALY_16000014
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#define ANOMALY_05000074 ANOMALY_16000015
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#define ANOMALY_05000416 ANOMALY_16000017
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#endif
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