273 lines
6.9 KiB
C
273 lines
6.9 KiB
C
/*
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* Clocksource driver for NXP LPC32xx/18xx/43xx timer
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*
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* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
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*
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* Based on:
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* time-efm32 Copyright (C) 2013 Pengutronix
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* mach-lpc32xx/timer.c Copyright (C) 2009 - 2010 NXP Semiconductors
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#define LPC32XX_TIMER_IR 0x000
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#define LPC32XX_TIMER_IR_MR0INT BIT(0)
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#define LPC32XX_TIMER_TCR 0x004
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#define LPC32XX_TIMER_TCR_CEN BIT(0)
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#define LPC32XX_TIMER_TCR_CRST BIT(1)
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#define LPC32XX_TIMER_TC 0x008
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#define LPC32XX_TIMER_PR 0x00c
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#define LPC32XX_TIMER_MCR 0x014
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#define LPC32XX_TIMER_MCR_MR0I BIT(0)
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#define LPC32XX_TIMER_MCR_MR0R BIT(1)
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#define LPC32XX_TIMER_MCR_MR0S BIT(2)
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#define LPC32XX_TIMER_MR0 0x018
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#define LPC32XX_TIMER_CTCR 0x070
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struct lpc32xx_clock_event_ddata {
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struct clock_event_device evtdev;
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void __iomem *base;
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};
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/* Needed for the sched clock */
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static void __iomem *clocksource_timer_counter;
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static u64 notrace lpc32xx_read_sched_clock(void)
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{
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return readl(clocksource_timer_counter);
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}
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static int lpc32xx_clkevt_next_event(unsigned long delta,
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struct clock_event_device *evtdev)
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{
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struct lpc32xx_clock_event_ddata *ddata =
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container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
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/*
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* Place timer in reset and program the delta in the prescale
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* register (PR). When the prescale counter matches the value
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* in PR the counter register is incremented and the compare
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* match will trigger. After setup the timer is released from
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* reset and enabled.
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*/
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writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
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writel_relaxed(delta, ddata->base + LPC32XX_TIMER_PR);
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writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
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return 0;
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}
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static int lpc32xx_clkevt_shutdown(struct clock_event_device *evtdev)
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{
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struct lpc32xx_clock_event_ddata *ddata =
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container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
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/* Disable the timer */
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writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
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return 0;
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}
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static int lpc32xx_clkevt_oneshot(struct clock_event_device *evtdev)
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{
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/*
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* When using oneshot, we must also disable the timer
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* to wait for the first call to set_next_event().
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*/
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return lpc32xx_clkevt_shutdown(evtdev);
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}
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static irqreturn_t lpc32xx_clock_event_handler(int irq, void *dev_id)
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{
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struct lpc32xx_clock_event_ddata *ddata = dev_id;
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/* Clear match on channel 0 */
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writel_relaxed(LPC32XX_TIMER_IR_MR0INT, ddata->base + LPC32XX_TIMER_IR);
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ddata->evtdev.event_handler(&ddata->evtdev);
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return IRQ_HANDLED;
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}
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static struct lpc32xx_clock_event_ddata lpc32xx_clk_event_ddata = {
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.evtdev = {
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.name = "lpc3220 clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 300,
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.set_next_event = lpc32xx_clkevt_next_event,
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.set_state_shutdown = lpc32xx_clkevt_shutdown,
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.set_state_oneshot = lpc32xx_clkevt_oneshot,
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},
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};
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static int __init lpc32xx_clocksource_init(struct device_node *np)
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{
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void __iomem *base;
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unsigned long rate;
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struct clk *clk;
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int ret;
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clk = of_clk_get_by_name(np, "timerclk");
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if (IS_ERR(clk)) {
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pr_err("clock get failed (%ld)\n", PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("clock enable failed (%d)\n", ret);
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goto err_clk_enable;
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}
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("unable to map registers\n");
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ret = -EADDRNOTAVAIL;
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goto err_iomap;
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}
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/*
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* Disable and reset timer then set it to free running timer
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* mode (CTCR) with no prescaler (PR) or match operations (MCR).
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* After setup the timer is released from reset and enabled.
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*/
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writel_relaxed(LPC32XX_TIMER_TCR_CRST, base + LPC32XX_TIMER_TCR);
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writel_relaxed(0, base + LPC32XX_TIMER_PR);
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writel_relaxed(0, base + LPC32XX_TIMER_MCR);
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writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
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writel_relaxed(LPC32XX_TIMER_TCR_CEN, base + LPC32XX_TIMER_TCR);
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rate = clk_get_rate(clk);
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ret = clocksource_mmio_init(base + LPC32XX_TIMER_TC, "lpc3220 timer",
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rate, 300, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("failed to init clocksource (%d)\n", ret);
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goto err_clocksource_init;
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}
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clocksource_timer_counter = base + LPC32XX_TIMER_TC;
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sched_clock_register(lpc32xx_read_sched_clock, 32, rate);
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return 0;
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err_clocksource_init:
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iounmap(base);
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err_iomap:
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clk_disable_unprepare(clk);
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err_clk_enable:
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clk_put(clk);
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return ret;
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}
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static int __init lpc32xx_clockevent_init(struct device_node *np)
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{
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void __iomem *base;
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unsigned long rate;
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struct clk *clk;
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int ret, irq;
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clk = of_clk_get_by_name(np, "timerclk");
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if (IS_ERR(clk)) {
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pr_err("clock get failed (%ld)\n", PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("clock enable failed (%d)\n", ret);
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goto err_clk_enable;
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}
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("unable to map registers\n");
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ret = -EADDRNOTAVAIL;
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goto err_iomap;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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pr_err("get irq failed\n");
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ret = -ENOENT;
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goto err_irq;
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}
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/*
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* Disable timer and clear any pending interrupt (IR) on match
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* channel 0 (MR0). Configure a compare match value of 1 on MR0
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* and enable interrupt, reset on match and stop on match (MCR).
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*/
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writel_relaxed(0, base + LPC32XX_TIMER_TCR);
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writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
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writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR);
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writel_relaxed(1, base + LPC32XX_TIMER_MR0);
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writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R |
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LPC32XX_TIMER_MCR_MR0S, base + LPC32XX_TIMER_MCR);
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rate = clk_get_rate(clk);
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lpc32xx_clk_event_ddata.base = base;
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clockevents_config_and_register(&lpc32xx_clk_event_ddata.evtdev,
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rate, 1, -1);
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ret = request_irq(irq, lpc32xx_clock_event_handler,
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IRQF_TIMER | IRQF_IRQPOLL, "lpc3220 clockevent",
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&lpc32xx_clk_event_ddata);
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if (ret) {
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pr_err("request irq failed\n");
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goto err_irq;
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}
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return 0;
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err_irq:
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iounmap(base);
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err_iomap:
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clk_disable_unprepare(clk);
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err_clk_enable:
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clk_put(clk);
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return ret;
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}
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/*
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* This function asserts that we have exactly one clocksource and one
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* clock_event_device in the end.
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*/
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static void __init lpc32xx_timer_init(struct device_node *np)
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{
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static int has_clocksource, has_clockevent;
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int ret;
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if (!has_clocksource) {
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ret = lpc32xx_clocksource_init(np);
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if (!ret) {
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has_clocksource = 1;
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return;
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}
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}
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if (!has_clockevent) {
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ret = lpc32xx_clockevent_init(np);
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if (!ret) {
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has_clockevent = 1;
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return;
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}
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}
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}
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CLOCKSOURCE_OF_DECLARE(lpc32xx_timer, "nxp,lpc3220-timer", lpc32xx_timer_init);
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