167 lines
5.7 KiB
C
167 lines
5.7 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "hdp_v4_0.h"
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#include "amdgpu_ras.h"
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#include "hdp/hdp_4_0_offset.h"
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#include "hdp/hdp_4_0_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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/* for Vega20 register name change */
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#define mmHDP_MEM_POWER_CTRL 0x00d4
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#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
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#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
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#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
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#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
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#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
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static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg)
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WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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else
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
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return;
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if (!ring || !ring->funcs->emit_wreg)
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WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
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else
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amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
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HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
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}
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static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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err_data->ue_count = 0;
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err_data->ce_count = 0;
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
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return;
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/* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
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err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
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};
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static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
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{
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
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return;
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if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
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WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
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else
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/*read back hdp ras counter to reset it to 0 */
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RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
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}
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static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
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adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
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adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
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adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
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def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
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data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
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else
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data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
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if (def != data)
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WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
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} else {
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def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
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data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
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HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
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HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
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HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
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else
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data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
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HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
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HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
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HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
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if (def != data)
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WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
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}
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}
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static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
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u32 *flags)
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{
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int data;
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/* AMD_CG_SUPPORT_HDP_LS */
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data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
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if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_HDP_LS;
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}
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static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
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{
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switch (adev->ip_versions[HDP_HWIP][0]) {
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case IP_VERSION(4, 2, 1):
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WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
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break;
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default:
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break;
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}
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WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
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WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
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WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
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}
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const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs = {
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.ras_late_init = amdgpu_hdp_ras_late_init,
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.ras_fini = amdgpu_hdp_ras_fini,
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.query_ras_error_count = hdp_v4_0_query_ras_error_count,
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.reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
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};
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const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
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.flush_hdp = hdp_v4_0_flush_hdp,
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.invalidate_hdp = hdp_v4_0_invalidate_hdp,
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.update_clock_gating = hdp_v4_0_update_clock_gating,
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.get_clock_gating_state = hdp_v4_0_get_clockgating_state,
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.init_registers = hdp_v4_0_init_registers,
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};
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