268 lines
6.0 KiB
C
268 lines
6.0 KiB
C
/*
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* OMAP4 specific common source file.
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/memblock.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include <asm/memblock.h>
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#include <plat/irqs.h>
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#include <plat/sram.h>
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#include <plat/omap-secure.h>
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#include <plat/mmc.h>
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#include <mach/hardware.h>
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#include <mach/omap-wakeupgen.h>
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#include "common.h"
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#include "hsmmc.h"
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#include "omap4-sar-layout.h"
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#include <linux/export.h>
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#ifdef CONFIG_CACHE_L2X0
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static void __iomem *l2cache_base;
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#endif
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static void __iomem *sar_ram_base;
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#ifdef CONFIG_OMAP4_ERRATA_I688
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/* Used to implement memory barrier on DRAM path */
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#define OMAP4_DRAM_BARRIER_VA 0xfe600000
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void __iomem *dram_sync, *sram_sync;
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static phys_addr_t paddr;
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static u32 size;
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void omap_bus_sync(void)
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{
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if (dram_sync && sram_sync) {
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writel_relaxed(readl_relaxed(dram_sync), dram_sync);
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writel_relaxed(readl_relaxed(sram_sync), sram_sync);
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isb();
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}
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}
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EXPORT_SYMBOL(omap_bus_sync);
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/* Steal one page physical memory for barrier implementation */
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int __init omap_barrier_reserve_memblock(void)
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{
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size = ALIGN(PAGE_SIZE, SZ_1M);
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paddr = arm_memblock_steal(size, SZ_1M);
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return 0;
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}
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void __init omap_barriers_init(void)
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{
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struct map_desc dram_io_desc[1];
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dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
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dram_io_desc[0].pfn = __phys_to_pfn(paddr);
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dram_io_desc[0].length = size;
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dram_io_desc[0].type = MT_MEMORY_SO;
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iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
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dram_sync = (void __iomem *) dram_io_desc[0].virtual;
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sram_sync = (void __iomem *) OMAP4_SRAM_VA;
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pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
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(long long) paddr, dram_io_desc[0].virtual);
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}
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#else
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void __init omap_barriers_init(void)
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{}
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#endif
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void __init gic_init_irq(void)
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{
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void __iomem *omap_irq_base;
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void __iomem *gic_dist_base_addr;
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/* Static mapping, never released */
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gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
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BUG_ON(!gic_dist_base_addr);
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/* Static mapping, never released */
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omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
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BUG_ON(!omap_irq_base);
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omap_wakeupgen_init();
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gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
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}
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *omap4_get_l2cache_base(void)
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{
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return l2cache_base;
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}
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static void omap4_l2x0_disable(void)
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{
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/* Disable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x0);
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}
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static void omap4_l2x0_set_debug(unsigned long val)
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{
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/* Program PL310 L2 Cache controller debug register */
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omap_smc1(0x100, val);
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}
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static int __init omap_l2_cache_init(void)
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{
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u32 aux_ctrl = 0;
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/*
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (!cpu_is_omap44xx())
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return -ENODEV;
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/* Static mapping, never released */
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l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
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if (WARN_ON(!l2cache_base))
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return -ENOMEM;
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/*
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* 16-way associativity, parity disabled
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* Way size - 32KB (es1.0)
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* Way size - 64KB (es2.0 +)
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*/
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aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
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(0x1 << 25) |
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(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
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(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
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} else {
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aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
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(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
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(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
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(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
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(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
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}
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if (omap_rev() != OMAP4430_REV_ES1_0)
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omap_smc1(0x109, aux_ctrl);
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/* Enable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x1);
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l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
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/*
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* Override default outer_cache.disable with a OMAP4
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* specific one
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*/
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outer_cache.disable = omap4_l2x0_disable;
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outer_cache.set_debug = omap4_l2x0_set_debug;
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return 0;
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}
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early_initcall(omap_l2_cache_init);
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#endif
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void __iomem *omap4_get_sar_ram_base(void)
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{
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return sar_ram_base;
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}
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/*
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* SAR RAM used to save and restore the HW
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* context in low power modes
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*/
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static int __init omap4_sar_ram_init(void)
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{
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/*
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (!cpu_is_omap44xx())
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return -ENOMEM;
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/* Static mapping, never released */
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sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
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if (WARN_ON(!sar_ram_base))
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return -ENOMEM;
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return 0;
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}
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early_initcall(omap4_sar_ram_init);
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#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
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static int omap4_twl6030_hsmmc_late_init(struct device *dev)
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{
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int irq = 0;
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struct platform_device *pdev = container_of(dev,
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struct platform_device, dev);
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struct omap_mmc_platform_data *pdata = dev->platform_data;
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/* Setting MMC1 Card detect Irq */
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if (pdev->id == 0) {
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irq = twl6030_mmc_card_detect_config();
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if (irq < 0) {
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dev_err(dev, "%s: Error card detect config(%d)\n",
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__func__, irq);
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return irq;
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}
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pdata->slots[0].card_detect_irq = irq;
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pdata->slots[0].card_detect = twl6030_mmc_card_detect;
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}
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return 0;
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}
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static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
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{
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struct omap_mmc_platform_data *pdata;
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/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
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if (!dev) {
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pr_err("Failed %s\n", __func__);
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return;
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}
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pdata = dev->platform_data;
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pdata->init = omap4_twl6030_hsmmc_late_init;
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}
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int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
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{
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struct omap2_hsmmc_info *c;
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omap_hsmmc_init(controllers);
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for (c = controllers; c->mmc; c++) {
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/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
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if (!c->pdev)
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continue;
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omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
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}
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return 0;
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}
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#else
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int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
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{
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return 0;
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}
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#endif
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