955 lines
24 KiB
C
955 lines
24 KiB
C
/*
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* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
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* using the CPU's debug registers.
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*
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* Copyright (C) 2012 ARM Limited
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* Author: Will Deacon <will.deacon@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) "hw-breakpoint: " fmt
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#include <linux/compat.h>
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#include <linux/cpu_pm.h>
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#include <linux/errno.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/perf_event.h>
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#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <asm/current.h>
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#include <asm/debug-monitors.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/kdebug.h>
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#include <asm/traps.h>
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#include <asm/cputype.h>
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#include <asm/system_misc.h>
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/* Breakpoint currently in use for each BRP. */
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static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
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/* Watchpoint currently in use for each WRP. */
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static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
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/* Currently stepping a per-CPU kernel breakpoint. */
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static DEFINE_PER_CPU(int, stepping_kernel_bp);
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/* Number of BRP/WRP registers on this CPU. */
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static int core_num_brps;
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static int core_num_wrps;
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/* Determine number of BRP registers available. */
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static int get_num_brps(void)
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{
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return ((read_cpuid(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
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}
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/* Determine number of WRP registers available. */
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static int get_num_wrps(void)
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{
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return ((read_cpuid(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
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}
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int hw_breakpoint_slots(int type)
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{
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/*
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* We can be called early, so don't rely on
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* our static variables being initialised.
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*/
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switch (type) {
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case TYPE_INST:
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return get_num_brps();
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case TYPE_DATA:
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return get_num_wrps();
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default:
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pr_warning("unknown slot type: %d\n", type);
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return 0;
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}
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}
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#define READ_WB_REG_CASE(OFF, N, REG, VAL) \
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case (OFF + N): \
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AARCH64_DBG_READ(N, REG, VAL); \
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break
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#define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
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case (OFF + N): \
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AARCH64_DBG_WRITE(N, REG, VAL); \
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break
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#define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
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READ_WB_REG_CASE(OFF, 0, REG, VAL); \
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READ_WB_REG_CASE(OFF, 1, REG, VAL); \
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READ_WB_REG_CASE(OFF, 2, REG, VAL); \
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READ_WB_REG_CASE(OFF, 3, REG, VAL); \
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READ_WB_REG_CASE(OFF, 4, REG, VAL); \
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READ_WB_REG_CASE(OFF, 5, REG, VAL); \
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READ_WB_REG_CASE(OFF, 6, REG, VAL); \
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READ_WB_REG_CASE(OFF, 7, REG, VAL); \
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READ_WB_REG_CASE(OFF, 8, REG, VAL); \
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READ_WB_REG_CASE(OFF, 9, REG, VAL); \
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READ_WB_REG_CASE(OFF, 10, REG, VAL); \
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READ_WB_REG_CASE(OFF, 11, REG, VAL); \
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READ_WB_REG_CASE(OFF, 12, REG, VAL); \
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READ_WB_REG_CASE(OFF, 13, REG, VAL); \
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READ_WB_REG_CASE(OFF, 14, REG, VAL); \
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READ_WB_REG_CASE(OFF, 15, REG, VAL)
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#define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
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WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
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WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
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static u64 read_wb_reg(int reg, int n)
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{
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u64 val = 0;
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switch (reg + n) {
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
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default:
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pr_warning("attempt to read from unknown breakpoint register %d\n", n);
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}
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return val;
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}
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static void write_wb_reg(int reg, int n, u64 val)
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{
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switch (reg + n) {
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
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default:
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pr_warning("attempt to write to unknown breakpoint register %d\n", n);
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}
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isb();
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}
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/*
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* Convert a breakpoint privilege level to the corresponding exception
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* level.
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*/
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static enum debug_el debug_exception_level(int privilege)
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{
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switch (privilege) {
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case AARCH64_BREAKPOINT_EL0:
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return DBG_ACTIVE_EL0;
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case AARCH64_BREAKPOINT_EL1:
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return DBG_ACTIVE_EL1;
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default:
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pr_warning("invalid breakpoint privilege level %d\n", privilege);
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return -EINVAL;
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}
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}
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enum hw_breakpoint_ops {
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HW_BREAKPOINT_INSTALL,
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HW_BREAKPOINT_UNINSTALL,
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HW_BREAKPOINT_RESTORE
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};
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/**
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* hw_breakpoint_slot_setup - Find and setup a perf slot according to
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* operations
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*
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* @slots: pointer to array of slots
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* @max_slots: max number of slots
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* @bp: perf_event to setup
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* @ops: operation to be carried out on the slot
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*
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* Return:
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* slot index on success
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* -ENOSPC if no slot is available/matches
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* -EINVAL on wrong operations parameter
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*/
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static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
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struct perf_event *bp,
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enum hw_breakpoint_ops ops)
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{
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int i;
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struct perf_event **slot;
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for (i = 0; i < max_slots; ++i) {
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slot = &slots[i];
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switch (ops) {
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case HW_BREAKPOINT_INSTALL:
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if (!*slot) {
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*slot = bp;
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return i;
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}
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break;
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case HW_BREAKPOINT_UNINSTALL:
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if (*slot == bp) {
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*slot = NULL;
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return i;
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}
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break;
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case HW_BREAKPOINT_RESTORE:
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if (*slot == bp)
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return i;
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break;
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default:
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pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
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return -EINVAL;
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}
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}
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return -ENOSPC;
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}
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static int hw_breakpoint_control(struct perf_event *bp,
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enum hw_breakpoint_ops ops)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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struct perf_event **slots;
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struct debug_info *debug_info = ¤t->thread.debug;
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int i, max_slots, ctrl_reg, val_reg, reg_enable;
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enum debug_el dbg_el = debug_exception_level(info->ctrl.privilege);
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u32 ctrl;
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if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
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/* Breakpoint */
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ctrl_reg = AARCH64_DBG_REG_BCR;
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val_reg = AARCH64_DBG_REG_BVR;
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slots = this_cpu_ptr(bp_on_reg);
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max_slots = core_num_brps;
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reg_enable = !debug_info->bps_disabled;
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} else {
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/* Watchpoint */
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ctrl_reg = AARCH64_DBG_REG_WCR;
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val_reg = AARCH64_DBG_REG_WVR;
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slots = this_cpu_ptr(wp_on_reg);
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max_slots = core_num_wrps;
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reg_enable = !debug_info->wps_disabled;
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}
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i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
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if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
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return i;
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switch (ops) {
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case HW_BREAKPOINT_INSTALL:
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/*
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* Ensure debug monitors are enabled at the correct exception
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* level.
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*/
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enable_debug_monitors(dbg_el);
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/* Fall through */
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case HW_BREAKPOINT_RESTORE:
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/* Setup the address register. */
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write_wb_reg(val_reg, i, info->address);
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/* Setup the control register. */
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ctrl = encode_ctrl_reg(info->ctrl);
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write_wb_reg(ctrl_reg, i,
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reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
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break;
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case HW_BREAKPOINT_UNINSTALL:
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/* Reset the control register. */
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write_wb_reg(ctrl_reg, i, 0);
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/*
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* Release the debug monitors for the correct exception
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* level.
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*/
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disable_debug_monitors(dbg_el);
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break;
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}
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return 0;
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}
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/*
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* Install a perf counter breakpoint.
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*/
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
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}
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
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}
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static int get_hbp_len(u8 hbp_len)
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{
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unsigned int len_in_bytes = 0;
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switch (hbp_len) {
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case ARM_BREAKPOINT_LEN_1:
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len_in_bytes = 1;
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break;
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case ARM_BREAKPOINT_LEN_2:
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len_in_bytes = 2;
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break;
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case ARM_BREAKPOINT_LEN_4:
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len_in_bytes = 4;
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break;
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case ARM_BREAKPOINT_LEN_8:
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len_in_bytes = 8;
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break;
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}
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return len_in_bytes;
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}
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/*
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* Check whether bp virtual address is in kernel space.
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*/
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int arch_check_bp_in_kernelspace(struct perf_event *bp)
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{
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unsigned int len;
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unsigned long va;
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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va = info->address;
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len = get_hbp_len(info->ctrl.len);
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return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
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}
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/*
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* Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
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* Hopefully this will disappear when ptrace can bypass the conversion
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* to generic breakpoint descriptions.
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*/
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int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
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int *gen_len, int *gen_type)
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{
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/* Type */
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switch (ctrl.type) {
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case ARM_BREAKPOINT_EXECUTE:
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*gen_type = HW_BREAKPOINT_X;
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break;
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case ARM_BREAKPOINT_LOAD:
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*gen_type = HW_BREAKPOINT_R;
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break;
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case ARM_BREAKPOINT_STORE:
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*gen_type = HW_BREAKPOINT_W;
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break;
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case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
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*gen_type = HW_BREAKPOINT_RW;
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break;
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default:
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return -EINVAL;
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}
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/* Len */
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switch (ctrl.len) {
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case ARM_BREAKPOINT_LEN_1:
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*gen_len = HW_BREAKPOINT_LEN_1;
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break;
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case ARM_BREAKPOINT_LEN_2:
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*gen_len = HW_BREAKPOINT_LEN_2;
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break;
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case ARM_BREAKPOINT_LEN_4:
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*gen_len = HW_BREAKPOINT_LEN_4;
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break;
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case ARM_BREAKPOINT_LEN_8:
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*gen_len = HW_BREAKPOINT_LEN_8;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Construct an arch_hw_breakpoint from a perf_event.
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*/
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static int arch_build_bp_info(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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/* Type */
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switch (bp->attr.bp_type) {
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case HW_BREAKPOINT_X:
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info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
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break;
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case HW_BREAKPOINT_R:
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info->ctrl.type = ARM_BREAKPOINT_LOAD;
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break;
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case HW_BREAKPOINT_W:
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info->ctrl.type = ARM_BREAKPOINT_STORE;
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break;
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case HW_BREAKPOINT_RW:
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info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
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break;
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default:
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return -EINVAL;
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}
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/* Len */
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switch (bp->attr.bp_len) {
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case HW_BREAKPOINT_LEN_1:
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info->ctrl.len = ARM_BREAKPOINT_LEN_1;
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break;
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case HW_BREAKPOINT_LEN_2:
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info->ctrl.len = ARM_BREAKPOINT_LEN_2;
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break;
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case HW_BREAKPOINT_LEN_4:
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info->ctrl.len = ARM_BREAKPOINT_LEN_4;
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break;
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case HW_BREAKPOINT_LEN_8:
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info->ctrl.len = ARM_BREAKPOINT_LEN_8;
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break;
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default:
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return -EINVAL;
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}
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/*
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* On AArch64, we only permit breakpoints of length 4, whereas
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* AArch32 also requires breakpoints of length 2 for Thumb.
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* Watchpoints can be of length 1, 2, 4 or 8 bytes.
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*/
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if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
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if (is_compat_task()) {
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if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
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info->ctrl.len != ARM_BREAKPOINT_LEN_4)
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return -EINVAL;
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} else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) {
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/*
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* FIXME: Some tools (I'm looking at you perf) assume
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* that breakpoints should be sizeof(long). This
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* is nonsense. For now, we fix up the parameter
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* but we should probably return -EINVAL instead.
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*/
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info->ctrl.len = ARM_BREAKPOINT_LEN_4;
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}
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}
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/* Address */
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info->address = bp->attr.bp_addr;
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/*
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* Privilege
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* Note that we disallow combined EL0/EL1 breakpoints because
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* that would complicate the stepping code.
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*/
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if (arch_check_bp_in_kernelspace(bp))
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info->ctrl.privilege = AARCH64_BREAKPOINT_EL1;
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else
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info->ctrl.privilege = AARCH64_BREAKPOINT_EL0;
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/* Enabled? */
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info->ctrl.enabled = !bp->attr.disabled;
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return 0;
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}
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/*
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* Validate the arch-specific HW Breakpoint register settings.
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*/
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int arch_validate_hwbkpt_settings(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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int ret;
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u64 alignment_mask, offset;
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/* Build the arch_hw_breakpoint. */
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ret = arch_build_bp_info(bp);
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if (ret)
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return ret;
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/*
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* Check address alignment.
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* We don't do any clever alignment correction for watchpoints
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* because using 64-bit unaligned addresses is deprecated for
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* AArch64.
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*
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* AArch32 tasks expect some simple alignment fixups, so emulate
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* that here.
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*/
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if (is_compat_task()) {
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if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
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alignment_mask = 0x7;
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else
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alignment_mask = 0x3;
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offset = info->address & alignment_mask;
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switch (offset) {
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case 0:
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/* Aligned */
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break;
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case 1:
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/* Allow single byte watchpoint. */
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if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
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break;
|
|
case 2:
|
|
/* Allow halfword watchpoints and breakpoints. */
|
|
if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
info->address &= ~alignment_mask;
|
|
info->ctrl.len <<= offset;
|
|
} else {
|
|
if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE)
|
|
alignment_mask = 0x3;
|
|
else
|
|
alignment_mask = 0x7;
|
|
if (info->address & alignment_mask)
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Disallow per-task kernel breakpoints since these would
|
|
* complicate the stepping code.
|
|
*/
|
|
if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.bp_target)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Enable/disable all of the breakpoints active at the specified
|
|
* exception level at the register level.
|
|
* This is used when single-stepping after a breakpoint exception.
|
|
*/
|
|
static void toggle_bp_registers(int reg, enum debug_el el, int enable)
|
|
{
|
|
int i, max_slots, privilege;
|
|
u32 ctrl;
|
|
struct perf_event **slots;
|
|
|
|
switch (reg) {
|
|
case AARCH64_DBG_REG_BCR:
|
|
slots = this_cpu_ptr(bp_on_reg);
|
|
max_slots = core_num_brps;
|
|
break;
|
|
case AARCH64_DBG_REG_WCR:
|
|
slots = this_cpu_ptr(wp_on_reg);
|
|
max_slots = core_num_wrps;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < max_slots; ++i) {
|
|
if (!slots[i])
|
|
continue;
|
|
|
|
privilege = counter_arch_bp(slots[i])->ctrl.privilege;
|
|
if (debug_exception_level(privilege) != el)
|
|
continue;
|
|
|
|
ctrl = read_wb_reg(reg, i);
|
|
if (enable)
|
|
ctrl |= 0x1;
|
|
else
|
|
ctrl &= ~0x1;
|
|
write_wb_reg(reg, i, ctrl);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Debug exception handlers.
|
|
*/
|
|
static int breakpoint_handler(unsigned long unused, unsigned int esr,
|
|
struct pt_regs *regs)
|
|
{
|
|
int i, step = 0, *kernel_step;
|
|
u32 ctrl_reg;
|
|
u64 addr, val;
|
|
struct perf_event *bp, **slots;
|
|
struct debug_info *debug_info;
|
|
struct arch_hw_breakpoint_ctrl ctrl;
|
|
|
|
slots = this_cpu_ptr(bp_on_reg);
|
|
addr = instruction_pointer(regs);
|
|
debug_info = ¤t->thread.debug;
|
|
|
|
for (i = 0; i < core_num_brps; ++i) {
|
|
rcu_read_lock();
|
|
|
|
bp = slots[i];
|
|
|
|
if (bp == NULL)
|
|
goto unlock;
|
|
|
|
/* Check if the breakpoint value matches. */
|
|
val = read_wb_reg(AARCH64_DBG_REG_BVR, i);
|
|
if (val != (addr & ~0x3))
|
|
goto unlock;
|
|
|
|
/* Possible match, check the byte address select to confirm. */
|
|
ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
|
|
decode_ctrl_reg(ctrl_reg, &ctrl);
|
|
if (!((1 << (addr & 0x3)) & ctrl.len))
|
|
goto unlock;
|
|
|
|
counter_arch_bp(bp)->trigger = addr;
|
|
perf_bp_event(bp, regs);
|
|
|
|
/* Do we need to handle the stepping? */
|
|
if (!bp->overflow_handler)
|
|
step = 1;
|
|
unlock:
|
|
rcu_read_unlock();
|
|
}
|
|
|
|
if (!step)
|
|
return 0;
|
|
|
|
if (user_mode(regs)) {
|
|
debug_info->bps_disabled = 1;
|
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0);
|
|
|
|
/* If we're already stepping a watchpoint, just return. */
|
|
if (debug_info->wps_disabled)
|
|
return 0;
|
|
|
|
if (test_thread_flag(TIF_SINGLESTEP))
|
|
debug_info->suspended_step = 1;
|
|
else
|
|
user_enable_single_step(current);
|
|
} else {
|
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0);
|
|
kernel_step = this_cpu_ptr(&stepping_kernel_bp);
|
|
|
|
if (*kernel_step != ARM_KERNEL_STEP_NONE)
|
|
return 0;
|
|
|
|
if (kernel_active_single_step()) {
|
|
*kernel_step = ARM_KERNEL_STEP_SUSPEND;
|
|
} else {
|
|
*kernel_step = ARM_KERNEL_STEP_ACTIVE;
|
|
kernel_enable_single_step(regs);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int watchpoint_handler(unsigned long addr, unsigned int esr,
|
|
struct pt_regs *regs)
|
|
{
|
|
int i, step = 0, *kernel_step, access;
|
|
u32 ctrl_reg;
|
|
u64 val, alignment_mask;
|
|
struct perf_event *wp, **slots;
|
|
struct debug_info *debug_info;
|
|
struct arch_hw_breakpoint *info;
|
|
struct arch_hw_breakpoint_ctrl ctrl;
|
|
|
|
slots = this_cpu_ptr(wp_on_reg);
|
|
debug_info = ¤t->thread.debug;
|
|
|
|
for (i = 0; i < core_num_wrps; ++i) {
|
|
rcu_read_lock();
|
|
|
|
wp = slots[i];
|
|
|
|
if (wp == NULL)
|
|
goto unlock;
|
|
|
|
info = counter_arch_bp(wp);
|
|
/* AArch32 watchpoints are either 4 or 8 bytes aligned. */
|
|
if (is_compat_task()) {
|
|
if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
|
|
alignment_mask = 0x7;
|
|
else
|
|
alignment_mask = 0x3;
|
|
} else {
|
|
alignment_mask = 0x7;
|
|
}
|
|
|
|
/* Check if the watchpoint value matches. */
|
|
val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
|
|
if (val != (addr & ~alignment_mask))
|
|
goto unlock;
|
|
|
|
/* Possible match, check the byte address select to confirm. */
|
|
ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
|
|
decode_ctrl_reg(ctrl_reg, &ctrl);
|
|
if (!((1 << (addr & alignment_mask)) & ctrl.len))
|
|
goto unlock;
|
|
|
|
/*
|
|
* Check that the access type matches.
|
|
* 0 => load, otherwise => store
|
|
*/
|
|
access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
|
|
HW_BREAKPOINT_R;
|
|
if (!(access & hw_breakpoint_type(wp)))
|
|
goto unlock;
|
|
|
|
info->trigger = addr;
|
|
perf_bp_event(wp, regs);
|
|
|
|
/* Do we need to handle the stepping? */
|
|
if (!wp->overflow_handler)
|
|
step = 1;
|
|
|
|
unlock:
|
|
rcu_read_unlock();
|
|
}
|
|
|
|
if (!step)
|
|
return 0;
|
|
|
|
/*
|
|
* We always disable EL0 watchpoints because the kernel can
|
|
* cause these to fire via an unprivileged access.
|
|
*/
|
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0);
|
|
|
|
if (user_mode(regs)) {
|
|
debug_info->wps_disabled = 1;
|
|
|
|
/* If we're already stepping a breakpoint, just return. */
|
|
if (debug_info->bps_disabled)
|
|
return 0;
|
|
|
|
if (test_thread_flag(TIF_SINGLESTEP))
|
|
debug_info->suspended_step = 1;
|
|
else
|
|
user_enable_single_step(current);
|
|
} else {
|
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0);
|
|
kernel_step = this_cpu_ptr(&stepping_kernel_bp);
|
|
|
|
if (*kernel_step != ARM_KERNEL_STEP_NONE)
|
|
return 0;
|
|
|
|
if (kernel_active_single_step()) {
|
|
*kernel_step = ARM_KERNEL_STEP_SUSPEND;
|
|
} else {
|
|
*kernel_step = ARM_KERNEL_STEP_ACTIVE;
|
|
kernel_enable_single_step(regs);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Handle single-step exception.
|
|
*/
|
|
int reinstall_suspended_bps(struct pt_regs *regs)
|
|
{
|
|
struct debug_info *debug_info = ¤t->thread.debug;
|
|
int handled_exception = 0, *kernel_step;
|
|
|
|
kernel_step = this_cpu_ptr(&stepping_kernel_bp);
|
|
|
|
/*
|
|
* Called from single-step exception handler.
|
|
* Return 0 if execution can resume, 1 if a SIGTRAP should be
|
|
* reported.
|
|
*/
|
|
if (user_mode(regs)) {
|
|
if (debug_info->bps_disabled) {
|
|
debug_info->bps_disabled = 0;
|
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1);
|
|
handled_exception = 1;
|
|
}
|
|
|
|
if (debug_info->wps_disabled) {
|
|
debug_info->wps_disabled = 0;
|
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
|
|
handled_exception = 1;
|
|
}
|
|
|
|
if (handled_exception) {
|
|
if (debug_info->suspended_step) {
|
|
debug_info->suspended_step = 0;
|
|
/* Allow exception handling to fall-through. */
|
|
handled_exception = 0;
|
|
} else {
|
|
user_disable_single_step(current);
|
|
}
|
|
}
|
|
} else if (*kernel_step != ARM_KERNEL_STEP_NONE) {
|
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1);
|
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1);
|
|
|
|
if (!debug_info->wps_disabled)
|
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
|
|
|
|
if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) {
|
|
kernel_disable_single_step();
|
|
handled_exception = 1;
|
|
} else {
|
|
handled_exception = 0;
|
|
}
|
|
|
|
*kernel_step = ARM_KERNEL_STEP_NONE;
|
|
}
|
|
|
|
return !handled_exception;
|
|
}
|
|
|
|
/*
|
|
* Context-switcher for restoring suspended breakpoints.
|
|
*/
|
|
void hw_breakpoint_thread_switch(struct task_struct *next)
|
|
{
|
|
/*
|
|
* current next
|
|
* disabled: 0 0 => The usual case, NOTIFY_DONE
|
|
* 0 1 => Disable the registers
|
|
* 1 0 => Enable the registers
|
|
* 1 1 => NOTIFY_DONE. per-task bps will
|
|
* get taken care of by perf.
|
|
*/
|
|
|
|
struct debug_info *current_debug_info, *next_debug_info;
|
|
|
|
current_debug_info = ¤t->thread.debug;
|
|
next_debug_info = &next->thread.debug;
|
|
|
|
/* Update breakpoints. */
|
|
if (current_debug_info->bps_disabled != next_debug_info->bps_disabled)
|
|
toggle_bp_registers(AARCH64_DBG_REG_BCR,
|
|
DBG_ACTIVE_EL0,
|
|
!next_debug_info->bps_disabled);
|
|
|
|
/* Update watchpoints. */
|
|
if (current_debug_info->wps_disabled != next_debug_info->wps_disabled)
|
|
toggle_bp_registers(AARCH64_DBG_REG_WCR,
|
|
DBG_ACTIVE_EL0,
|
|
!next_debug_info->wps_disabled);
|
|
}
|
|
|
|
/*
|
|
* CPU initialisation.
|
|
*/
|
|
static void hw_breakpoint_reset(void *unused)
|
|
{
|
|
int i;
|
|
struct perf_event **slots;
|
|
/*
|
|
* When a CPU goes through cold-boot, it does not have any installed
|
|
* slot, so it is safe to share the same function for restoring and
|
|
* resetting breakpoints; when a CPU is hotplugged in, it goes
|
|
* through the slots, which are all empty, hence it just resets control
|
|
* and value for debug registers.
|
|
* When this function is triggered on warm-boot through a CPU PM
|
|
* notifier some slots might be initialized; if so they are
|
|
* reprogrammed according to the debug slots content.
|
|
*/
|
|
for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) {
|
|
if (slots[i]) {
|
|
hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
|
|
} else {
|
|
write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
|
|
write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
|
|
}
|
|
}
|
|
|
|
for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) {
|
|
if (slots[i]) {
|
|
hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
|
|
} else {
|
|
write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
|
|
write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int hw_breakpoint_reset_notify(struct notifier_block *self,
|
|
unsigned long action,
|
|
void *hcpu)
|
|
{
|
|
int cpu = (long)hcpu;
|
|
if (action == CPU_ONLINE)
|
|
smp_call_function_single(cpu, hw_breakpoint_reset, NULL, 1);
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block hw_breakpoint_reset_nb = {
|
|
.notifier_call = hw_breakpoint_reset_notify,
|
|
};
|
|
|
|
#ifdef CONFIG_CPU_PM
|
|
extern void cpu_suspend_set_dbg_restorer(void (*hw_bp_restore)(void *));
|
|
#else
|
|
static inline void cpu_suspend_set_dbg_restorer(void (*hw_bp_restore)(void *))
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* One-time initialisation.
|
|
*/
|
|
static int __init arch_hw_breakpoint_init(void)
|
|
{
|
|
core_num_brps = get_num_brps();
|
|
core_num_wrps = get_num_wrps();
|
|
|
|
pr_info("found %d breakpoint and %d watchpoint registers.\n",
|
|
core_num_brps, core_num_wrps);
|
|
|
|
cpu_notifier_register_begin();
|
|
|
|
/*
|
|
* Reset the breakpoint resources. We assume that a halting
|
|
* debugger will leave the world in a nice state for us.
|
|
*/
|
|
smp_call_function(hw_breakpoint_reset, NULL, 1);
|
|
hw_breakpoint_reset(NULL);
|
|
|
|
/* Register debug fault handlers. */
|
|
hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP,
|
|
TRAP_HWBKPT, "hw-breakpoint handler");
|
|
hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP,
|
|
TRAP_HWBKPT, "hw-watchpoint handler");
|
|
|
|
/* Register hotplug notifier. */
|
|
__register_cpu_notifier(&hw_breakpoint_reset_nb);
|
|
|
|
cpu_notifier_register_done();
|
|
|
|
/* Register cpu_suspend hw breakpoint restore hook */
|
|
cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(arch_hw_breakpoint_init);
|
|
|
|
void hw_breakpoint_pmu_read(struct perf_event *bp)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Dummy function to register with die_notifier.
|
|
*/
|
|
int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
|
|
unsigned long val, void *data)
|
|
{
|
|
return NOTIFY_DONE;
|
|
}
|