123 lines
3.7 KiB
C
123 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _LINUX_CACHEINFO_H
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#define _LINUX_CACHEINFO_H
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#include <linux/bitops.h>
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#include <linux/cpumask.h>
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#include <linux/smp.h>
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struct device_node;
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struct attribute;
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enum cache_type {
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CACHE_TYPE_NOCACHE = 0,
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CACHE_TYPE_INST = BIT(0),
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CACHE_TYPE_DATA = BIT(1),
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CACHE_TYPE_SEPARATE = CACHE_TYPE_INST | CACHE_TYPE_DATA,
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CACHE_TYPE_UNIFIED = BIT(2),
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};
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extern unsigned int coherency_max_size;
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/**
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* struct cacheinfo - represent a cache leaf node
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* @id: This cache's id. It is unique among caches with the same (type, level).
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* @type: type of the cache - data, inst or unified
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* @level: represents the hierarchy in the multi-level cache
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* @coherency_line_size: size of each cache line usually representing
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* the minimum amount of data that gets transferred from memory
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* @number_of_sets: total number of sets, a set is a collection of cache
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* lines sharing the same index
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* @ways_of_associativity: number of ways in which a particular memory
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* block can be placed in the cache
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* @physical_line_partition: number of physical cache lines sharing the
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* same cachetag
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* @size: Total size of the cache
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* @shared_cpu_map: logical cpumask representing all the cpus sharing
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* this cache node
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* @attributes: bitfield representing various cache attributes
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* @fw_token: Unique value used to determine if different cacheinfo
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* structures represent a single hardware cache instance.
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* @disable_sysfs: indicates whether this node is visible to the user via
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* sysfs or not
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* @priv: pointer to any private data structure specific to particular
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* cache design
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*
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* While @of_node, @disable_sysfs and @priv are used for internal book
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* keeping, the remaining members form the core properties of the cache
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*/
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struct cacheinfo {
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unsigned int id;
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enum cache_type type;
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unsigned int level;
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unsigned int coherency_line_size;
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unsigned int number_of_sets;
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unsigned int ways_of_associativity;
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unsigned int physical_line_partition;
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unsigned int size;
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cpumask_t shared_cpu_map;
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unsigned int attributes;
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#define CACHE_WRITE_THROUGH BIT(0)
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#define CACHE_WRITE_BACK BIT(1)
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#define CACHE_WRITE_POLICY_MASK \
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(CACHE_WRITE_THROUGH | CACHE_WRITE_BACK)
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#define CACHE_READ_ALLOCATE BIT(2)
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#define CACHE_WRITE_ALLOCATE BIT(3)
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#define CACHE_ALLOCATE_POLICY_MASK \
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(CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE)
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#define CACHE_ID BIT(4)
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void *fw_token;
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bool disable_sysfs;
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void *priv;
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};
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struct cpu_cacheinfo {
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struct cacheinfo *info_list;
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unsigned int num_levels;
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unsigned int num_leaves;
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bool cpu_map_populated;
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};
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/*
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* Helpers to make sure "func" is executed on the cpu whose cache
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* attributes are being detected
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*/
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#define DEFINE_SMP_CALL_CACHE_FUNCTION(func) \
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static inline void _##func(void *ret) \
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{ \
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int cpu = smp_processor_id(); \
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*(int *)ret = __##func(cpu); \
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} \
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\
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int func(unsigned int cpu) \
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{ \
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int ret; \
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smp_call_function_single(cpu, _##func, &ret, true); \
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return ret; \
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}
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struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
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int init_cache_level(unsigned int cpu);
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int populate_cache_leaves(unsigned int cpu);
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int cache_setup_acpi(unsigned int cpu);
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#ifndef CONFIG_ACPI_PPTT
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/*
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* acpi_find_last_cache_level is only called on ACPI enabled
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* platforms using the PPTT for topology. This means that if
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* the platform supports other firmware configuration methods
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* we need to stub out the call when ACPI is disabled.
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* ACPI enabled platforms not using PPTT won't be making calls
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* to this function so we need not worry about them.
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*/
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static inline int acpi_find_last_cache_level(unsigned int cpu)
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{
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return 0;
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}
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#else
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int acpi_find_last_cache_level(unsigned int cpu);
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#endif
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const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf);
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#endif /* _LINUX_CACHEINFO_H */
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