132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright Sunplus Technology Co., Ltd.
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* All rights reserved.
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*/
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#include <linux/platform_device.h>
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#include <linux/netdevice.h>
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#include <linux/bitfield.h>
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#include <linux/of_mdio.h>
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#include "spl2sw_register.h"
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#include "spl2sw_define.h"
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#include "spl2sw_mdio.h"
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#define SPL2SW_MDIO_READ_CMD 0x02
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#define SPL2SW_MDIO_WRITE_CMD 0x01
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static int spl2sw_mdio_access(struct spl2sw_common *comm, u8 cmd, u8 addr, u8 regnum, u16 wdata)
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{
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u32 reg, reg2;
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u32 val;
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int ret;
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/* Note that addr (of phy) should match either ext_phy0_addr
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* or ext_phy1_addr, or mdio commands won't be sent out.
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*/
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reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
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reg &= ~MAC_EXT_PHY0_ADDR;
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reg |= FIELD_PREP(MAC_EXT_PHY0_ADDR, addr);
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reg2 = FIELD_PREP(MAC_CPU_PHY_WT_DATA, wdata) | FIELD_PREP(MAC_CPU_PHY_CMD, cmd) |
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FIELD_PREP(MAC_CPU_PHY_REG_ADDR, regnum) | FIELD_PREP(MAC_CPU_PHY_ADDR, addr);
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/* Set ext_phy0_addr and then issue mdio command.
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* No interrupt is allowed in between.
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*/
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spin_lock_irq(&comm->mdio_lock);
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writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
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writel(reg2, comm->l2sw_reg_base + L2SW_PHY_CNTL_REG0);
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spin_unlock_irq(&comm->mdio_lock);
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ret = read_poll_timeout(readl, val, val & cmd, 1, 1000, true,
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comm->l2sw_reg_base + L2SW_PHY_CNTL_REG1);
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/* Set ext_phy0_addr back to 31 to prevent
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* from sending mdio command to phy by
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* hardware auto-mdio function.
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*/
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reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
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reg &= ~MAC_EXT_PHY0_ADDR;
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reg |= FIELD_PREP(MAC_EXT_PHY0_ADDR, 31);
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writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
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if (ret == 0)
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return val >> 16;
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else
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return ret;
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}
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static int spl2sw_mii_read(struct mii_bus *bus, int addr, int regnum)
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{
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struct spl2sw_common *comm = bus->priv;
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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return spl2sw_mdio_access(comm, SPL2SW_MDIO_READ_CMD, addr, regnum, 0);
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}
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static int spl2sw_mii_write(struct mii_bus *bus, int addr, int regnum, u16 val)
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{
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struct spl2sw_common *comm = bus->priv;
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int ret;
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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ret = spl2sw_mdio_access(comm, SPL2SW_MDIO_WRITE_CMD, addr, regnum, val);
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if (ret < 0)
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return ret;
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return 0;
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}
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u32 spl2sw_mdio_init(struct spl2sw_common *comm)
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{
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struct device_node *mdio_np;
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struct mii_bus *mii_bus;
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int ret;
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/* Get mdio child node. */
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mdio_np = of_get_child_by_name(comm->pdev->dev.of_node, "mdio");
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if (!mdio_np) {
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dev_err(&comm->pdev->dev, "No mdio child node found!\n");
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return -ENODEV;
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}
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/* Allocate and register mdio bus. */
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mii_bus = devm_mdiobus_alloc(&comm->pdev->dev);
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if (!mii_bus) {
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ret = -ENOMEM;
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goto out;
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}
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mii_bus->name = "sunplus_mii_bus";
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mii_bus->parent = &comm->pdev->dev;
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mii_bus->priv = comm;
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mii_bus->read = spl2sw_mii_read;
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mii_bus->write = spl2sw_mii_write;
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snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&comm->pdev->dev));
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ret = of_mdiobus_register(mii_bus, mdio_np);
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if (ret) {
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dev_err(&comm->pdev->dev, "Failed to register mdiobus!\n");
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goto out;
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}
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comm->mii_bus = mii_bus;
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out:
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of_node_put(mdio_np);
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return ret;
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}
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void spl2sw_mdio_remove(struct spl2sw_common *comm)
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{
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if (comm->mii_bus) {
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mdiobus_unregister(comm->mii_bus);
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comm->mii_bus = NULL;
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}
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}
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