359 lines
8.7 KiB
C
359 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* pata-cs5530.c - CS5530 PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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*
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* based upon cs5530.c by Mark Lord.
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*
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* Loosely based on the piix & svwks drivers.
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*
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* Documentation:
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* Available from AMD web site.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/dmi.h>
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#define DRV_NAME "pata_cs5530"
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#define DRV_VERSION "0.7.4"
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static void __iomem *cs5530_port_base(struct ata_port *ap)
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{
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unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;
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return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no);
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}
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/**
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* cs5530_set_piomode - PIO setup
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* @ap: ATA interface
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* @adev: device on the interface
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*
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* Set our PIO requirements. This is fairly simple on the CS5530
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* chips.
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*/
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static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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static const unsigned int cs5530_pio_timings[2][5] = {
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{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
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{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
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};
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void __iomem *base = cs5530_port_base(ap);
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u32 tuning;
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int format;
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/* Find out which table to use */
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tuning = ioread32(base + 0x04);
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format = (tuning & 0x80000000UL) ? 1 : 0;
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/* Now load the right timing register */
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if (adev->devno)
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base += 0x08;
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iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
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}
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/**
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* cs5530_set_dmamode - DMA timing setup
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* @ap: ATA interface
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* @adev: Device being configured
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*
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* We cannot mix MWDMA and UDMA without reloading timings each switch
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* master to slave. We track the last DMA setup in order to minimise
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* reloads.
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*/
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static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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void __iomem *base = cs5530_port_base(ap);
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u32 tuning, timing = 0;
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u8 reg;
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/* Find out which table to use */
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tuning = ioread32(base + 0x04);
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switch(adev->dma_mode) {
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case XFER_UDMA_0:
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timing = 0x00921250;break;
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case XFER_UDMA_1:
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timing = 0x00911140;break;
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case XFER_UDMA_2:
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timing = 0x00911030;break;
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case XFER_MW_DMA_0:
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timing = 0x00077771;break;
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case XFER_MW_DMA_1:
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timing = 0x00012121;break;
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case XFER_MW_DMA_2:
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timing = 0x00002020;break;
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default:
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BUG();
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}
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/* Merge in the PIO format bit */
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timing |= (tuning & 0x80000000UL);
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if (adev->devno == 0) /* Master */
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iowrite32(timing, base + 0x04);
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else {
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if (timing & 0x00100000)
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tuning |= 0x00100000; /* UDMA for both */
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else
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tuning &= ~0x00100000; /* MWDMA for both */
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iowrite32(tuning, base + 0x04);
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iowrite32(timing, base + 0x0C);
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}
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/* Set the DMA capable bit in the BMDMA area */
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reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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reg |= (1 << (5 + adev->devno));
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iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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/* Remember the last DMA setup we did */
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ap->private_data = adev;
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}
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/**
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* cs5530_qc_issue - command issue
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* @qc: command pending
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*
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* Called when the libata layer is about to issue a command. We wrap
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* this interface so that we can load the correct ATA timings if
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* necessary. Specifically we have a problem that there is only
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* one MWDMA/UDMA bit.
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*/
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static unsigned int cs5530_qc_issue(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_device *prev = ap->private_data;
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/* See if the DMA settings could be wrong */
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if (ata_dma_enabled(adev) && adev != prev && prev != NULL) {
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/* Maybe, but do the channels match MWDMA/UDMA ? */
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if ((ata_using_udma(adev) && !ata_using_udma(prev)) ||
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(ata_using_udma(prev) && !ata_using_udma(adev)))
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/* Switch the mode bits */
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cs5530_set_dmamode(ap, adev);
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}
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return ata_bmdma_qc_issue(qc);
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}
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static struct scsi_host_template cs5530_sht = {
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ATA_BASE_SHT(DRV_NAME),
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.sg_tablesize = LIBATA_DUMB_MAX_PRD,
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.dma_boundary = ATA_DMA_BOUNDARY,
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};
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static struct ata_port_operations cs5530_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.qc_prep = ata_bmdma_dumb_qc_prep,
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.qc_issue = cs5530_qc_issue,
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.cable_detect = ata_cable_40wire,
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.set_piomode = cs5530_set_piomode,
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.set_dmamode = cs5530_set_dmamode,
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};
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static const struct dmi_system_id palmax_dmi_table[] = {
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{
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.ident = "Palmax PD1100",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
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},
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},
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{ }
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};
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static int cs5530_is_palmax(void)
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{
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if (dmi_check_system(palmax_dmi_table)) {
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printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
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return 1;
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}
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return 0;
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}
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/**
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* cs5530_init_chip - Chipset init
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*
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* Perform the chip initialisation work that is shared between both
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* setup and resume paths
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*/
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static int cs5530_init_chip(void)
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{
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struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL;
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while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
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switch (dev->device) {
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case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
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master_0 = pci_dev_get(dev);
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break;
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case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
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cs5530_0 = pci_dev_get(dev);
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break;
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}
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}
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if (!master_0) {
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printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
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goto fail_put;
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}
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if (!cs5530_0) {
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printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
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goto fail_put;
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}
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pci_set_master(cs5530_0);
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pci_try_set_mwi(cs5530_0);
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/*
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* Set PCI CacheLineSize to 16-bytes:
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* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
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*
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* Note: This value is constant because the 5530 is only a Geode companion
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*/
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pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
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/*
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* Disable trapping of UDMA register accesses (Win98 hack):
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* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
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*/
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pci_write_config_word(cs5530_0, 0xd0, 0x5006);
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/*
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* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
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* The other settings are what is necessary to get the register
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* into a sane state for IDE DMA operation.
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*/
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pci_write_config_byte(master_0, 0x40, 0x1e);
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/*
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* Set max PCI burst size (16-bytes seems to work best):
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* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
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* all others: clear bit-1 at 0x41, and do:
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* 128bytes: OR 0x00 at 0x41
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* 256bytes: OR 0x04 at 0x41
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* 512bytes: OR 0x08 at 0x41
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* 1024bytes: OR 0x0c at 0x41
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*/
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pci_write_config_byte(master_0, 0x41, 0x14);
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/*
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* These settings are necessary to get the chip
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* into a sane state for IDE DMA operation.
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*/
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pci_write_config_byte(master_0, 0x42, 0x00);
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pci_write_config_byte(master_0, 0x43, 0xc1);
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pci_dev_put(master_0);
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pci_dev_put(cs5530_0);
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return 0;
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fail_put:
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pci_dev_put(master_0);
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pci_dev_put(cs5530_0);
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return -ENODEV;
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}
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/**
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* cs5530_init_one - Initialise a CS5530
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* @pdev: PCI device
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* @id: Entry in match table
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*
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* Install a driver for the newly found CS5530 companion chip. Most of
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* this is just housekeeping. We have to set the chip up correctly and
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* turn off various bits of emulation magic.
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*/
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static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static const struct ata_port_info info = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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.port_ops = &cs5530_port_ops
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};
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/* The docking connector doesn't do UDMA, and it seems not MWDMA */
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static const struct ata_port_info info_palmax_secondary = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.port_ops = &cs5530_port_ops
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};
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const struct ata_port_info *ppi[] = { &info, NULL };
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int rc;
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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/* Chip initialisation */
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if (cs5530_init_chip())
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return -ENODEV;
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if (cs5530_is_palmax())
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ppi[1] = &info_palmax_secondary;
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/* Now kick off ATA set up */
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return ata_pci_bmdma_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
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}
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#ifdef CONFIG_PM_SLEEP
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static int cs5530_reinit_one(struct pci_dev *pdev)
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{
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struct ata_host *host = pci_get_drvdata(pdev);
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int rc;
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rc = ata_pci_device_do_resume(pdev);
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if (rc)
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return rc;
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/* If we fail on resume we are doomed */
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if (cs5530_init_chip())
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return -EIO;
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ata_host_resume(host);
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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static const struct pci_device_id cs5530[] = {
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{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
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{ },
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};
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static struct pci_driver cs5530_pci_driver = {
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.name = DRV_NAME,
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.id_table = cs5530,
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.probe = cs5530_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM_SLEEP
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.suspend = ata_pci_device_suspend,
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.resume = cs5530_reinit_one,
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#endif
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};
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module_pci_driver(cs5530_pci_driver);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, cs5530);
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MODULE_VERSION(DRV_VERSION);
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