886 lines
26 KiB
C
886 lines
26 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/module.h>
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#include <linux/fdtable.h>
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#include <linux/uaccess.h>
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_ucode.h"
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#include "gfx_v8_0.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#include "gca/gfx_8_0_d.h"
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#include "gca/gfx_8_0_enum.h"
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#include "oss/oss_3_0_sh_mask.h"
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#include "oss/oss_3_0_d.h"
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#include "gmc/gmc_8_1_sh_mask.h"
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#include "gmc/gmc_8_1_d.h"
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#include "vi_structs.h"
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#include "vid.h"
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enum hqd_dequeue_request_type {
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NO_ACTION = 0,
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DRAIN_PIPE,
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RESET_WAVES
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};
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struct vi_sdma_mqd;
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/*
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* Register access functions
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*/
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases);
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid);
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static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr,
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uint32_t wptr_shift, uint32_t wptr_mask,
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struct mm_struct *mm);
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static int kgd_hqd_dump(struct kgd_dev *kgd,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs);
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static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
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uint32_t __user *wptr, struct mm_struct *mm);
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static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
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uint32_t engine_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs);
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static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
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uint32_t pipe_id, uint32_t queue_id);
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static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
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static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
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enum kfd_preempt_type reset_type,
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unsigned int utimeout, uint32_t pipe_id,
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uint32_t queue_id);
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static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
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unsigned int utimeout);
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static int kgd_address_watch_disable(struct kgd_dev *kgd);
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static int kgd_address_watch_execute(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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uint32_t cntl_val,
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uint32_t addr_hi,
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uint32_t addr_lo);
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static int kgd_wave_control_execute(struct kgd_dev *kgd,
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uint32_t gfx_index_val,
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uint32_t sq_cmd);
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static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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unsigned int reg_offset);
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static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
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uint8_t vmid);
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static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
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uint8_t vmid);
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static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
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static void set_scratch_backing_va(struct kgd_dev *kgd,
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uint64_t va, uint32_t vmid);
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static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t page_table_base);
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static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
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static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
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/* Because of REG_GET_FIELD() being used, we put this function in the
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* asic specific file.
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*/
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static int get_tile_config(struct kgd_dev *kgd,
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struct tile_config *config)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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config->gb_addr_config = adev->gfx.config.gb_addr_config;
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config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
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MC_ARB_RAMCFG, NOOFBANK);
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config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
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MC_ARB_RAMCFG, NOOFRANKS);
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config->tile_config_ptr = adev->gfx.config.tile_mode_array;
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config->num_tile_configs =
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ARRAY_SIZE(adev->gfx.config.tile_mode_array);
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config->macro_tile_config_ptr =
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adev->gfx.config.macrotile_mode_array;
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config->num_macro_tile_configs =
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ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
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return 0;
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}
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static const struct kfd2kgd_calls kfd2kgd = {
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.init_gtt_mem_allocation = alloc_gtt_mem,
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.free_gtt_mem = free_gtt_mem,
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.get_local_mem_info = get_local_mem_info,
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.get_gpu_clock_counter = get_gpu_clock_counter,
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.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
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.alloc_pasid = amdgpu_pasid_alloc,
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.free_pasid = amdgpu_pasid_free,
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.program_sh_mem_settings = kgd_program_sh_mem_settings,
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.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
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.init_interrupts = kgd_init_interrupts,
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.hqd_load = kgd_hqd_load,
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.hqd_sdma_load = kgd_hqd_sdma_load,
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.hqd_dump = kgd_hqd_dump,
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.hqd_sdma_dump = kgd_hqd_sdma_dump,
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.hqd_is_occupied = kgd_hqd_is_occupied,
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.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
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.hqd_destroy = kgd_hqd_destroy,
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.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
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.address_watch_disable = kgd_address_watch_disable,
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.address_watch_execute = kgd_address_watch_execute,
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.wave_control_execute = kgd_wave_control_execute,
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.address_watch_get_offset = kgd_address_watch_get_offset,
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.get_atc_vmid_pasid_mapping_pasid =
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get_atc_vmid_pasid_mapping_pasid,
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.get_atc_vmid_pasid_mapping_valid =
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get_atc_vmid_pasid_mapping_valid,
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.get_fw_version = get_fw_version,
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.set_scratch_backing_va = set_scratch_backing_va,
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.get_tile_config = get_tile_config,
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.get_cu_info = get_cu_info,
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.get_vram_usage = amdgpu_amdkfd_get_vram_usage,
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.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
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.acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
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.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
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.release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
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.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
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.set_vm_context_page_table_base = set_vm_context_page_table_base,
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.alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
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.free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
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.map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
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.unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
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.sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
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.map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
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.restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
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.invalidate_tlbs = invalidate_tlbs,
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.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
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.submit_ib = amdgpu_amdkfd_submit_ib,
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.get_vm_fault_info = amdgpu_amdkfd_gpuvm_get_vm_fault_info,
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.gpu_recover = amdgpu_amdkfd_gpu_reset,
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.set_compute_idle = amdgpu_amdkfd_set_compute_idle
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};
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struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
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{
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return (struct kfd2kgd_calls *)&kfd2kgd;
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}
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static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
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{
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return (struct amdgpu_device *)kgd;
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}
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static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
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uint32_t queue, uint32_t vmid)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
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mutex_lock(&adev->srbm_mutex);
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WREG32(mmSRBM_GFX_CNTL, value);
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}
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static void unlock_srbm(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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WREG32(mmSRBM_GFX_CNTL, 0);
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mutex_unlock(&adev->srbm_mutex);
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}
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static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t queue_id)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(kgd, mec, pipe, queue_id, 0);
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}
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static void release_queue(struct kgd_dev *kgd)
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{
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unlock_srbm(kgd);
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}
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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lock_srbm(kgd, 0, 0, 0, vmid);
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WREG32(mmSH_MEM_CONFIG, sh_mem_config);
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WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
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WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
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WREG32(mmSH_MEM_BASES, sh_mem_bases);
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unlock_srbm(kgd);
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}
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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/*
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* We have to assume that there is no outstanding mapping.
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* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
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* a mapping is in progress or because a mapping finished
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* and the SW cleared it.
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* So the protocol is to always wait & clear.
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*/
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uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
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ATC_VMID0_PASID_MAPPING__VALID_MASK;
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WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
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while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
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cpu_relax();
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WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
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/* Mapping vmid to pasid also for IH block */
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WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
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return 0;
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}
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static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t mec;
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uint32_t pipe;
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mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(kgd, mec, pipe, 0, 0);
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WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);
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unlock_srbm(kgd);
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return 0;
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}
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static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
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{
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uint32_t retval;
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retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
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m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
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pr_debug("kfd: sdma base address: 0x%x\n", retval);
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return retval;
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}
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static inline struct vi_mqd *get_mqd(void *mqd)
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{
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return (struct vi_mqd *)mqd;
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}
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static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
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{
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return (struct vi_sdma_mqd *)mqd;
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}
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr,
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uint32_t wptr_shift, uint32_t wptr_mask,
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struct mm_struct *mm)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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struct vi_mqd *m;
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uint32_t *mqd_hqd;
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uint32_t reg, wptr_val, data;
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bool valid_wptr = false;
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m = get_mqd(mqd);
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acquire_queue(kgd, pipe_id, queue_id);
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/* HIQ is set during driver init period with vmid set to 0*/
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if (m->cp_hqd_vmid == 0) {
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uint32_t value, mec, pipe;
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mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
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mec, pipe, queue_id);
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value = RREG32(mmRLC_CP_SCHEDULERS);
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value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
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((mec << 5) | (pipe << 3) | queue_id | 0x80));
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WREG32(mmRLC_CP_SCHEDULERS, value);
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}
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/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
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mqd_hqd = &m->cp_mqd_base_addr_lo;
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for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
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WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
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/* Tonga errata: EOP RPTR/WPTR should be left unmodified.
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* This is safe since EOP RPTR==WPTR for any inactive HQD
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* on ASICs that do not support context-save.
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* EOP writes/reads can start anywhere in the ring.
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*/
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if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) {
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WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
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WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
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WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
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}
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for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
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WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
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/* Copy userspace write pointer value to register.
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* Activate doorbell logic to monitor subsequent changes.
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*/
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data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
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CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
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WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
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/* read_user_ptr may take the mm->mmap_sem.
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* release srbm_mutex to avoid circular dependency between
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* srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
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*/
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release_queue(kgd);
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valid_wptr = read_user_wptr(mm, wptr, wptr_val);
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acquire_queue(kgd, pipe_id, queue_id);
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if (valid_wptr)
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WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
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data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
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WREG32(mmCP_HQD_ACTIVE, data);
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release_queue(kgd);
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return 0;
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}
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static int kgd_hqd_dump(struct kgd_dev *kgd,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t i = 0, reg;
|
|
#define HQD_N_REGS (54+4)
|
|
#define DUMP_REG(addr) do { \
|
|
if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
|
|
break; \
|
|
(*dump)[i][0] = (addr) << 2; \
|
|
(*dump)[i++][1] = RREG32(addr); \
|
|
} while (0)
|
|
|
|
*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
|
|
if (*dump == NULL)
|
|
return -ENOMEM;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
|
|
DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
|
|
DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
|
|
DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
|
|
DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
|
|
|
|
for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
|
|
DUMP_REG(reg);
|
|
|
|
release_queue(kgd);
|
|
|
|
WARN_ON_ONCE(i != HQD_N_REGS);
|
|
*n_regs = i;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
|
|
uint32_t __user *wptr, struct mm_struct *mm)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
struct vi_sdma_mqd *m;
|
|
unsigned long end_jiffies;
|
|
uint32_t sdma_base_addr;
|
|
uint32_t data;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
|
|
m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
|
|
|
|
end_jiffies = msecs_to_jiffies(2000) + jiffies;
|
|
while (true) {
|
|
data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
|
|
if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
|
|
break;
|
|
if (time_after(jiffies, end_jiffies))
|
|
return -ETIME;
|
|
usleep_range(500, 1000);
|
|
}
|
|
if (m->sdma_engine_id) {
|
|
data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
|
|
data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
|
|
RESUME_CTX, 0);
|
|
WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
|
|
} else {
|
|
data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
|
|
data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
|
|
RESUME_CTX, 0);
|
|
WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
|
|
}
|
|
|
|
data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
|
|
ENABLE, 1);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
|
|
|
|
if (read_user_wptr(mm, wptr, data))
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
|
|
else
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
|
|
m->sdmax_rlcx_rb_rptr);
|
|
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
|
|
m->sdmax_rlcx_virtual_addr);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
|
|
m->sdmax_rlcx_rb_base_hi);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
|
|
m->sdmax_rlcx_rb_rptr_addr_lo);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
|
|
m->sdmax_rlcx_rb_rptr_addr_hi);
|
|
|
|
data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
|
|
RB_ENABLE, 1);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
|
|
uint32_t engine_id, uint32_t queue_id,
|
|
uint32_t (**dump)[2], uint32_t *n_regs)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
|
|
queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
|
|
uint32_t i = 0, reg;
|
|
#undef HQD_N_REGS
|
|
#define HQD_N_REGS (19+4+2+3+7)
|
|
|
|
*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
|
|
if (*dump == NULL)
|
|
return -ENOMEM;
|
|
|
|
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
|
|
DUMP_REG(sdma_offset + reg);
|
|
for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
|
|
reg++)
|
|
DUMP_REG(sdma_offset + reg);
|
|
for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
|
|
reg++)
|
|
DUMP_REG(sdma_offset + reg);
|
|
for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
|
|
reg++)
|
|
DUMP_REG(sdma_offset + reg);
|
|
for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
|
|
reg++)
|
|
DUMP_REG(sdma_offset + reg);
|
|
|
|
WARN_ON_ONCE(i != HQD_N_REGS);
|
|
*n_regs = i;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
|
|
uint32_t pipe_id, uint32_t queue_id)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t act;
|
|
bool retval = false;
|
|
uint32_t low, high;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
act = RREG32(mmCP_HQD_ACTIVE);
|
|
if (act) {
|
|
low = lower_32_bits(queue_address >> 8);
|
|
high = upper_32_bits(queue_address >> 8);
|
|
|
|
if (low == RREG32(mmCP_HQD_PQ_BASE) &&
|
|
high == RREG32(mmCP_HQD_PQ_BASE_HI))
|
|
retval = true;
|
|
}
|
|
release_queue(kgd);
|
|
return retval;
|
|
}
|
|
|
|
static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
struct vi_sdma_mqd *m;
|
|
uint32_t sdma_base_addr;
|
|
uint32_t sdma_rlc_rb_cntl;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
|
|
sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
|
|
|
|
if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
|
|
enum kfd_preempt_type reset_type,
|
|
unsigned int utimeout, uint32_t pipe_id,
|
|
uint32_t queue_id)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t temp;
|
|
enum hqd_dequeue_request_type type;
|
|
unsigned long flags, end_jiffies;
|
|
int retry;
|
|
struct vi_mqd *m = get_mqd(mqd);
|
|
|
|
if (adev->in_gpu_reset)
|
|
return -EIO;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
|
|
if (m->cp_hqd_vmid == 0)
|
|
WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
|
|
|
|
switch (reset_type) {
|
|
case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
|
|
type = DRAIN_PIPE;
|
|
break;
|
|
case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
|
|
type = RESET_WAVES;
|
|
break;
|
|
default:
|
|
type = DRAIN_PIPE;
|
|
break;
|
|
}
|
|
|
|
/* Workaround: If IQ timer is active and the wait time is close to or
|
|
* equal to 0, dequeueing is not safe. Wait until either the wait time
|
|
* is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
|
|
* cleared before continuing. Also, ensure wait times are set to at
|
|
* least 0x3.
|
|
*/
|
|
local_irq_save(flags);
|
|
preempt_disable();
|
|
retry = 5000; /* wait for 500 usecs at maximum */
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_IQ_TIMER);
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
|
|
pr_debug("HW is processing IQ\n");
|
|
goto loop;
|
|
}
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
|
|
== 3) /* SEM-rearm is safe */
|
|
break;
|
|
/* Wait time 3 is safe for CP, but our MMIO read/write
|
|
* time is close to 1 microsecond, so check for 10 to
|
|
* leave more buffer room
|
|
*/
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
|
|
>= 10)
|
|
break;
|
|
pr_debug("IQ timer is active\n");
|
|
} else
|
|
break;
|
|
loop:
|
|
if (!retry) {
|
|
pr_err("CP HQD IQ timer status time out\n");
|
|
break;
|
|
}
|
|
ndelay(100);
|
|
--retry;
|
|
}
|
|
retry = 1000;
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
|
|
if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
|
|
break;
|
|
pr_debug("Dequeue request is pending\n");
|
|
|
|
if (!retry) {
|
|
pr_err("CP HQD dequeue request time out\n");
|
|
break;
|
|
}
|
|
ndelay(100);
|
|
--retry;
|
|
}
|
|
local_irq_restore(flags);
|
|
preempt_enable();
|
|
|
|
WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
|
|
|
|
end_jiffies = (utimeout * HZ / 1000) + jiffies;
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_ACTIVE);
|
|
if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
|
|
break;
|
|
if (time_after(jiffies, end_jiffies)) {
|
|
pr_err("cp queue preemption time out.\n");
|
|
release_queue(kgd);
|
|
return -ETIME;
|
|
}
|
|
usleep_range(500, 1000);
|
|
}
|
|
|
|
release_queue(kgd);
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
|
|
unsigned int utimeout)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
struct vi_sdma_mqd *m;
|
|
uint32_t sdma_base_addr;
|
|
uint32_t temp;
|
|
unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
|
|
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
|
|
temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
|
|
|
|
while (true) {
|
|
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
|
|
if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
|
|
break;
|
|
if (time_after(jiffies, end_jiffies))
|
|
return -ETIME;
|
|
usleep_range(500, 1000);
|
|
}
|
|
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
|
|
RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
|
|
SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
|
|
|
|
m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
|
|
uint8_t vmid)
|
|
{
|
|
uint32_t reg;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
|
|
return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
|
|
}
|
|
|
|
static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
|
|
uint8_t vmid)
|
|
{
|
|
uint32_t reg;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
|
|
return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
|
|
}
|
|
|
|
static int kgd_address_watch_disable(struct kgd_dev *kgd)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_address_watch_execute(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
uint32_t cntl_val,
|
|
uint32_t addr_hi,
|
|
uint32_t addr_lo)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_wave_control_execute(struct kgd_dev *kgd,
|
|
uint32_t gfx_index_val,
|
|
uint32_t sq_cmd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t data = 0;
|
|
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
|
|
WREG32(mmSQ_CMD, sq_cmd);
|
|
|
|
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
|
|
INSTANCE_BROADCAST_WRITES, 1);
|
|
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
|
|
SH_BROADCAST_WRITES, 1);
|
|
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
|
|
SE_BROADCAST_WRITES, 1);
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, data);
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
unsigned int reg_offset)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void set_scratch_backing_va(struct kgd_dev *kgd,
|
|
uint64_t va, uint32_t vmid)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
lock_srbm(kgd, 0, 0, 0, vmid);
|
|
WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
|
|
unlock_srbm(kgd);
|
|
}
|
|
|
|
static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
const union amdgpu_firmware_header *hdr;
|
|
|
|
switch (type) {
|
|
case KGD_ENGINE_PFP:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.pfp_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_ME:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.me_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_CE:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.ce_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC1:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.mec_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC2:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.mec2_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_RLC:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.rlc_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_SDMA1:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->sdma.instance[0].fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_SDMA2:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->sdma.instance[1].fw->data;
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
if (hdr == NULL)
|
|
return 0;
|
|
|
|
/* Only 12 bit in use*/
|
|
return hdr->common.ucode_version;
|
|
}
|
|
|
|
static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
|
|
uint32_t page_table_base)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
|
|
if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
|
|
pr_err("trying to set page table base for wrong VMID\n");
|
|
return;
|
|
}
|
|
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
|
|
}
|
|
|
|
static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
int vmid;
|
|
unsigned int tmp;
|
|
|
|
if (adev->in_gpu_reset)
|
|
return -EIO;
|
|
|
|
for (vmid = 0; vmid < 16; vmid++) {
|
|
if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
|
|
continue;
|
|
|
|
tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
|
|
if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
|
|
(tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
|
|
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
|
|
RREG32(mmVM_INVALIDATE_RESPONSE);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
|
|
pr_err("non kfd vmid %d\n", vmid);
|
|
return -EINVAL;
|
|
}
|
|
|
|
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
|
|
RREG32(mmVM_INVALIDATE_RESPONSE);
|
|
return 0;
|
|
}
|