328 lines
10 KiB
C
328 lines
10 KiB
C
/* linux/drivers/usb/phy/phy-samsung-usb.h
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
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* OHCI-EXYNOS controllers.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/usb/phy.h>
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/* Register definitions */
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#define SAMSUNG_PHYPWR (0x00)
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#define PHYPWR_NORMAL_MASK (0x19 << 0)
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#define PHYPWR_OTG_DISABLE (0x1 << 4)
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#define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
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#define PHYPWR_FORCE_SUSPEND (0x1 << 1)
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/* For Exynos4 */
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#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
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#define PHYPWR_SLEEP_PHY0 (0x1 << 5)
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#define SAMSUNG_PHYCLK (0x04)
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#define PHYCLK_MODE_USB11 (0x1 << 6)
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#define PHYCLK_EXT_OSC (0x1 << 5)
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#define PHYCLK_COMMON_ON_N (0x1 << 4)
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#define PHYCLK_ID_PULL (0x1 << 2)
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#define PHYCLK_CLKSEL_MASK (0x3 << 0)
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#define PHYCLK_CLKSEL_48M (0x0 << 0)
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#define PHYCLK_CLKSEL_12M (0x2 << 0)
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#define PHYCLK_CLKSEL_24M (0x3 << 0)
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#define SAMSUNG_RSTCON (0x08)
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#define RSTCON_PHYLINK_SWRST (0x1 << 2)
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#define RSTCON_HLINK_SWRST (0x1 << 1)
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#define RSTCON_SWRST (0x1 << 0)
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/* EXYNOS5 */
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#define EXYNOS5_PHY_HOST_CTRL0 (0x00)
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#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
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#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
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#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
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#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
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#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
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#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
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#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
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#define FSEL_CLKSEL_50M (0x7)
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#define FSEL_CLKSEL_24M (0x5)
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#define FSEL_CLKSEL_20M (0x4)
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#define FSEL_CLKSEL_19200K (0x3)
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#define FSEL_CLKSEL_12M (0x2)
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#define FSEL_CLKSEL_10M (0x1)
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#define FSEL_CLKSEL_9600K (0x0)
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#define HOST_CTRL0_TESTBURNIN (0x1 << 11)
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#define HOST_CTRL0_RETENABLE (0x1 << 10)
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#define HOST_CTRL0_COMMONON_N (0x1 << 9)
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#define HOST_CTRL0_SIDDQ (0x1 << 6)
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#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
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#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
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#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
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#define HOST_CTRL0_UTMISWRST (0x1 << 2)
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#define HOST_CTRL0_LINKSWRST (0x1 << 1)
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#define HOST_CTRL0_PHYSWRST (0x1 << 0)
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#define EXYNOS5_PHY_HOST_TUNE0 (0x04)
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#define EXYNOS5_PHY_HSIC_CTRL1 (0x10)
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#define EXYNOS5_PHY_HSIC_TUNE1 (0x14)
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#define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
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#define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
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#define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
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#define HSIC_CTRL_REFCLKSEL (0x2 << 23)
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#define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
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#define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
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#define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
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#define HSIC_CTRL_REFCLKDIV_15 (0x1c << 16)
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#define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
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#define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
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#define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
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#define HSIC_CTRL_SIDDQ (0x1 << 6)
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#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
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#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
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#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
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#define HSIC_CTRL_UTMISWRST (0x1 << 2)
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#define HSIC_CTRL_PHYSWRST (0x1 << 0)
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#define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
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#define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
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#define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
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#define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
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#define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
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#define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
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#define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
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#define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
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#define HOST_OHCICTRL_CNTSEL (0x1 << 1)
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#define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
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#define EXYNOS5_PHY_OTG_SYS (0x38)
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#define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
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#define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
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#define OTG_SYS_PHY0_SWRST (0x1 << 12)
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#define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
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#define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
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#define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
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#define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
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#define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
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#define OTG_SYS_COMMON_ON (0x1 << 7)
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#define OTG_SYS_FSEL_MASK (0x7 << 4)
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#define OTG_SYS_FSEL(_x) ((_x) << 4)
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#define OTG_SYS_FORCESLEEP (0x1 << 3)
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#define OTG_SYS_OTGDISABLE (0x1 << 2)
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#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
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#define OTG_SYS_FORCESUSPEND (0x1 << 0)
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#define EXYNOS5_PHY_OTG_TUNE (0x40)
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/* EXYNOS5: USB 3.0 DRD */
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#define EXYNOS5_DRD_LINKSYSTEM (0x04)
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
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#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
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#define EXYNOS5_DRD_PHYUTMI (0x08)
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#define PHYUTMI_OTGDISABLE (0x1 << 6)
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#define PHYUTMI_FORCESUSPEND (0x1 << 1)
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#define PHYUTMI_FORCESLEEP (0x1 << 0)
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#define EXYNOS5_DRD_PHYPIPE (0x0c)
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#define EXYNOS5_DRD_PHYCLKRST (0x10)
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#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
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#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
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#define PHYCLKRST_SSC_EN (0x1 << 20)
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#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
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#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
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#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
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#define PHYCLKRST_FSEL_MASK (0x3f << 5)
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#define PHYCLKRST_FSEL(_x) ((_x) << 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
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#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
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#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
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#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
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#define PHYCLKRST_RETENABLEN (0x1 << 4)
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#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
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#define PHYCLKRST_PORTRESET (0x1 << 1)
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#define PHYCLKRST_COMMONONN (0x1 << 0)
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#define EXYNOS5_DRD_PHYREG0 (0x14)
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#define EXYNOS5_DRD_PHYREG1 (0x18)
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#define EXYNOS5_DRD_PHYPARAM0 (0x1c)
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#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
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#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
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#define EXYNOS5_DRD_PHYPARAM1 (0x20)
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#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
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#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
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#define EXYNOS5_DRD_PHYTERM (0x24)
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#define EXYNOS5_DRD_PHYTEST (0x28)
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#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
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#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
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#define EXYNOS5_DRD_PHYADP (0x2c)
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#define EXYNOS5_DRD_PHYBATCHG (0x30)
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#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
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#define EXYNOS5_DRD_PHYRESUME (0x34)
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#define EXYNOS5_DRD_LINKPORT (0x44)
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#ifndef MHZ
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#define MHZ (1000*1000)
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#endif
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#ifndef KHZ
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#define KHZ (1000)
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#endif
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#define EXYNOS_USBHOST_PHY_CTRL_OFFSET (0x4)
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#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
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#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
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#define EXYNOS_USB20PHY_CFG_HOST_LINK (0x1 << 0)
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enum samsung_cpu_type {
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TYPE_S3C64XX,
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TYPE_EXYNOS4210,
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TYPE_EXYNOS5250,
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};
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/*
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* struct samsung_usbphy_drvdata - driver data for various SoC variants
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* @cpu_type: machine identifier
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* @devphy_en_mask: device phy enable mask for PHY CONTROL register
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* @hostphy_en_mask: host phy enable mask for PHY CONTROL register
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* @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
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* mapped address of system controller.
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* @hostphy_reg_offset: offset to HOST PHY CONTROL register from
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* mapped address of system controller.
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*
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* Here we have a separate mask for device type phy.
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* Having different masks for host and device type phy helps
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* in setting independent masks in case of SoCs like S5PV210,
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* in which PHY0 and PHY1 enable bits belong to same register
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* placed at position 0 and 1 respectively.
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* Although for newer SoCs like exynos these bits belong to
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* different registers altogether placed at position 0.
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*/
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struct samsung_usbphy_drvdata {
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int cpu_type;
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int devphy_en_mask;
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int hostphy_en_mask;
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u32 devphy_reg_offset;
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u32 hostphy_reg_offset;
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};
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/*
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* struct samsung_usbphy - transceiver driver state
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* @phy: transceiver structure
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* @plat: platform data
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* @dev: The parent device supplied to the probe function
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* @clk: usb phy clock
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* @regs: usb phy controller registers memory base
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* @pmuregs: USB device PHY_CONTROL register memory base
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* @sysreg: USB2.0 PHY_CFG register memory base
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* @ref_clk_freq: reference clock frequency selection
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* @drv_data: driver data available for different SoCs
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* @phy_type: Samsung SoCs specific phy types: #HOST
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* #DEVICE
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* @phy_usage: usage count for phy
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* @lock: lock for phy operations
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*/
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struct samsung_usbphy {
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struct usb_phy phy;
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struct samsung_usbphy_data *plat;
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struct device *dev;
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struct clk *clk;
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void __iomem *regs;
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void __iomem *pmuregs;
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void __iomem *sysreg;
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int ref_clk_freq;
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const struct samsung_usbphy_drvdata *drv_data;
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enum samsung_usb_phy_type phy_type;
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atomic_t phy_usage;
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spinlock_t lock;
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};
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#define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
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static const struct of_device_id samsung_usbphy_dt_match[];
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static inline const struct samsung_usbphy_drvdata
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*samsung_usbphy_get_driver_data(struct platform_device *pdev)
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{
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if (pdev->dev.of_node) {
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const struct of_device_id *match;
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match = of_match_node(samsung_usbphy_dt_match,
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pdev->dev.of_node);
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return match->data;
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}
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return (struct samsung_usbphy_drvdata *)
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platform_get_device_id(pdev)->driver_data;
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}
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extern int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy);
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extern void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on);
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extern void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy);
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extern int samsung_usbphy_set_type(struct usb_phy *phy,
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enum samsung_usb_phy_type phy_type);
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extern int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy);
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