482 lines
14 KiB
C
482 lines
14 KiB
C
/*
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* Copyright © 2014-2018 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef _V3D_DRM_H_
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#define _V3D_DRM_H_
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define DRM_V3D_SUBMIT_CL 0x00
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#define DRM_V3D_WAIT_BO 0x01
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#define DRM_V3D_CREATE_BO 0x02
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#define DRM_V3D_MMAP_BO 0x03
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#define DRM_V3D_GET_PARAM 0x04
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#define DRM_V3D_GET_BO_OFFSET 0x05
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#define DRM_V3D_SUBMIT_TFU 0x06
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#define DRM_V3D_SUBMIT_CSD 0x07
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#define DRM_V3D_PERFMON_CREATE 0x08
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#define DRM_V3D_PERFMON_DESTROY 0x09
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#define DRM_V3D_PERFMON_GET_VALUES 0x0a
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#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
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#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
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#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
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#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
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#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
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#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
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#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
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#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
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#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
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struct drm_v3d_perfmon_create)
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#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
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struct drm_v3d_perfmon_destroy)
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#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
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struct drm_v3d_perfmon_get_values)
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#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
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#define DRM_V3D_SUBMIT_EXTENSION 0x02
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/* struct drm_v3d_extension - ioctl extensions
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*
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* Linked-list of generic extensions where the id identify which struct is
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* pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
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* the extension type.
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*/
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struct drm_v3d_extension {
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__u64 next;
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__u32 id;
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#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
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__u32 flags; /* mbz */
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};
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/* struct drm_v3d_sem - wait/signal semaphore
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*
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* If binary semaphore, it only takes syncobj handle and ignores flags and
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* point fields. Point is defined for timeline syncobj feature.
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*/
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struct drm_v3d_sem {
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__u32 handle; /* syncobj */
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/* rsv below, for future uses */
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__u32 flags;
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__u64 point; /* for timeline sem support */
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__u64 mbz[2]; /* must be zero, rsv */
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};
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/* Enum for each of the V3D queues. */
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enum v3d_queue {
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V3D_BIN,
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V3D_RENDER,
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V3D_TFU,
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V3D_CSD,
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V3D_CACHE_CLEAN,
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};
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/**
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* struct drm_v3d_multi_sync - ioctl extension to add support multiples
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* syncobjs for commands submission.
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*
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* When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
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* this extension to define wait and signal dependencies, instead of single
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* in/out sync entries on submitting commands. The field flags is used to
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* determine the stage to set wait dependencies.
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*/
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struct drm_v3d_multi_sync {
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struct drm_v3d_extension base;
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/* Array of wait and signal semaphores */
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__u64 in_syncs;
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__u64 out_syncs;
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/* Number of entries */
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__u32 in_sync_count;
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__u32 out_sync_count;
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/* set the stage (v3d_queue) to sync */
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__u32 wait_stage;
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__u32 pad; /* mbz */
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};
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/**
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* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
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* engine.
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*
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* This asks the kernel to have the GPU execute an optional binner
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* command list, and a render command list.
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*
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* The L1T, slice, L2C, L2T, and GCA caches will be flushed before
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* each CL executes. The VCD cache should be flushed (if necessary)
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* by the submitted CLs. The TLB writes are guaranteed to have been
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* flushed by the time the render done IRQ happens, which is the
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* trigger for out_sync. Any dirtying of cachelines by the job (only
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* possible using TMU writes) must be flushed by the caller using the
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* DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
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*/
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struct drm_v3d_submit_cl {
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/* Pointer to the binner command list.
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*
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* This is the first set of commands executed, which runs the
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* coordinate shader to determine where primitives land on the screen,
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* then writes out the state updates and draw calls necessary per tile
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* to the tile allocation BO.
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*
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* This BCL will block on any previous BCL submitted on the
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* same FD, but not on any RCL or BCLs submitted by other
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* clients -- that is left up to the submitter to control
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* using in_sync_bcl if necessary.
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*/
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__u32 bcl_start;
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/** End address of the BCL (first byte after the BCL) */
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__u32 bcl_end;
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/* Offset of the render command list.
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*
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* This is the second set of commands executed, which will either
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* execute the tiles that have been set up by the BCL, or a fixed set
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* of tiles (in the case of RCL-only blits).
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*
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* This RCL will block on this submit's BCL, and any previous
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* RCL submitted on the same FD, but not on any RCL or BCLs
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* submitted by other clients -- that is left up to the
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* submitter to control using in_sync_rcl if necessary.
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*/
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__u32 rcl_start;
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/** End address of the RCL (first byte after the RCL) */
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__u32 rcl_end;
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/** An optional sync object to wait on before starting the BCL. */
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__u32 in_sync_bcl;
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/** An optional sync object to wait on before starting the RCL. */
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__u32 in_sync_rcl;
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/** An optional sync object to place the completion fence in. */
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__u32 out_sync;
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/* Offset of the tile alloc memory
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*
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* This is optional on V3D 3.3 (where the CL can set the value) but
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* required on V3D 4.1.
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*/
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__u32 qma;
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/** Size of the tile alloc memory. */
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__u32 qms;
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/** Offset of the tile state data array. */
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__u32 qts;
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/* Pointer to a u32 array of the BOs that are referenced by the job.
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*/
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__u64 bo_handles;
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/* Number of BO handles passed in (size is that times 4). */
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__u32 bo_handle_count;
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/* DRM_V3D_SUBMIT_* properties */
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__u32 flags;
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/* ID of the perfmon to attach to this job. 0 means no perfmon. */
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__u32 perfmon_id;
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__u32 pad;
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/* Pointer to an array of ioctl extensions*/
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__u64 extensions;
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};
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/**
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* struct drm_v3d_wait_bo - ioctl argument for waiting for
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* completion of the last DRM_V3D_SUBMIT_CL on a BO.
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*
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* This is useful for cases where multiple processes might be
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* rendering to a BO and you want to wait for all rendering to be
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* completed.
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*/
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struct drm_v3d_wait_bo {
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__u32 handle;
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__u32 pad;
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__u64 timeout_ns;
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};
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/**
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* struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
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*
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* There are currently no values for the flags argument, but it may be
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* used in a future extension.
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*/
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struct drm_v3d_create_bo {
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__u32 size;
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__u32 flags;
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/** Returned GEM handle for the BO. */
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__u32 handle;
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/**
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* Returned offset for the BO in the V3D address space. This offset
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* is private to the DRM fd and is valid for the lifetime of the GEM
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* handle.
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*
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* This offset value will always be nonzero, since various HW
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* units treat 0 specially.
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*/
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__u32 offset;
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};
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/**
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* struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
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*
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* This doesn't actually perform an mmap. Instead, it returns the
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* offset you need to use in an mmap on the DRM device node. This
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* means that tools like valgrind end up knowing about the mapped
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* memory.
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*
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* There are currently no values for the flags argument, but it may be
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* used in a future extension.
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*/
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struct drm_v3d_mmap_bo {
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/** Handle for the object being mapped. */
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__u32 handle;
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__u32 flags;
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/** offset into the drm node to use for subsequent mmap call. */
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__u64 offset;
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};
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enum drm_v3d_param {
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DRM_V3D_PARAM_V3D_UIFCFG,
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DRM_V3D_PARAM_V3D_HUB_IDENT1,
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DRM_V3D_PARAM_V3D_HUB_IDENT2,
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DRM_V3D_PARAM_V3D_HUB_IDENT3,
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DRM_V3D_PARAM_V3D_CORE0_IDENT0,
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DRM_V3D_PARAM_V3D_CORE0_IDENT1,
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DRM_V3D_PARAM_V3D_CORE0_IDENT2,
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DRM_V3D_PARAM_SUPPORTS_TFU,
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DRM_V3D_PARAM_SUPPORTS_CSD,
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DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
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DRM_V3D_PARAM_SUPPORTS_PERFMON,
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DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
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};
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struct drm_v3d_get_param {
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__u32 param;
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__u32 pad;
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__u64 value;
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};
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/**
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* Returns the offset for the BO in the V3D address space for this DRM fd.
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* This is the same value returned by drm_v3d_create_bo, if that was called
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* from this DRM fd.
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*/
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struct drm_v3d_get_bo_offset {
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__u32 handle;
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__u32 offset;
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};
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struct drm_v3d_submit_tfu {
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__u32 icfg;
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__u32 iia;
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__u32 iis;
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__u32 ica;
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__u32 iua;
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__u32 ioa;
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__u32 ios;
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__u32 coef[4];
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/* First handle is the output BO, following are other inputs.
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* 0 for unused.
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*/
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__u32 bo_handles[4];
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/* sync object to block on before running the TFU job. Each TFU
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* job will execute in the order submitted to its FD. Synchronization
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* against rendering jobs requires using sync objects.
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*/
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__u32 in_sync;
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/* Sync object to signal when the TFU job is done. */
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__u32 out_sync;
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__u32 flags;
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/* Pointer to an array of ioctl extensions*/
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__u64 extensions;
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};
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/* Submits a compute shader for dispatch. This job will block on any
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* previous compute shaders submitted on this fd, and any other
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* synchronization must be performed with in_sync/out_sync.
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*/
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struct drm_v3d_submit_csd {
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__u32 cfg[7];
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__u32 coef[4];
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/* Pointer to a u32 array of the BOs that are referenced by the job.
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*/
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__u64 bo_handles;
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/* Number of BO handles passed in (size is that times 4). */
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__u32 bo_handle_count;
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/* sync object to block on before running the CSD job. Each
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* CSD job will execute in the order submitted to its FD.
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* Synchronization against rendering/TFU jobs or CSD from
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* other fds requires using sync objects.
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*/
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__u32 in_sync;
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/* Sync object to signal when the CSD job is done. */
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__u32 out_sync;
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/* ID of the perfmon to attach to this job. 0 means no perfmon. */
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__u32 perfmon_id;
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/* Pointer to an array of ioctl extensions*/
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__u64 extensions;
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__u32 flags;
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__u32 pad;
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};
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enum {
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V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
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V3D_PERFCNT_FEP_VALID_PRIMS,
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V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
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V3D_PERFCNT_FEP_VALID_QUADS,
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V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
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V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
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V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
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V3D_PERFCNT_TLB_QUADS_ZERO_COV,
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V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
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V3D_PERFCNT_TLB_QUADS_WRITTEN,
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V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
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V3D_PERFCNT_PTB_PRIM_CLIP,
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V3D_PERFCNT_PTB_PRIM_REV,
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V3D_PERFCNT_QPU_IDLE_CYCLES,
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V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
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V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
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V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
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V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
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V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
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V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
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V3D_PERFCNT_QPU_IC_HIT,
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V3D_PERFCNT_QPU_IC_MISS,
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V3D_PERFCNT_QPU_UC_HIT,
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V3D_PERFCNT_QPU_UC_MISS,
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V3D_PERFCNT_TMU_TCACHE_ACCESS,
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V3D_PERFCNT_TMU_TCACHE_MISS,
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V3D_PERFCNT_VPM_VDW_STALL,
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V3D_PERFCNT_VPM_VCD_STALL,
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V3D_PERFCNT_BIN_ACTIVE,
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V3D_PERFCNT_RDR_ACTIVE,
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V3D_PERFCNT_L2T_HITS,
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V3D_PERFCNT_L2T_MISSES,
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V3D_PERFCNT_CYCLE_COUNT,
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V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
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V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
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V3D_PERFCNT_PTB_PRIMS_BINNED,
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V3D_PERFCNT_AXI_WRITES_WATCH_0,
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V3D_PERFCNT_AXI_READS_WATCH_0,
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V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
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V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
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V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
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V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
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V3D_PERFCNT_AXI_WRITES_WATCH_1,
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V3D_PERFCNT_AXI_READS_WATCH_1,
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V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
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V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
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V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
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V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
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V3D_PERFCNT_TLB_PARTIAL_QUADS,
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V3D_PERFCNT_TMU_CONFIG_ACCESSES,
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V3D_PERFCNT_L2T_NO_ID_STALL,
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V3D_PERFCNT_L2T_COM_QUE_STALL,
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V3D_PERFCNT_L2T_TMU_WRITES,
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V3D_PERFCNT_TMU_ACTIVE_CYCLES,
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V3D_PERFCNT_TMU_STALLED_CYCLES,
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V3D_PERFCNT_CLE_ACTIVE,
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V3D_PERFCNT_L2T_TMU_READS,
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V3D_PERFCNT_L2T_CLE_READS,
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V3D_PERFCNT_L2T_VCD_READS,
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V3D_PERFCNT_L2T_TMUCFG_READS,
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V3D_PERFCNT_L2T_SLC0_READS,
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V3D_PERFCNT_L2T_SLC1_READS,
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V3D_PERFCNT_L2T_SLC2_READS,
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V3D_PERFCNT_L2T_TMU_W_MISSES,
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V3D_PERFCNT_L2T_TMU_R_MISSES,
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V3D_PERFCNT_L2T_CLE_MISSES,
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V3D_PERFCNT_L2T_VCD_MISSES,
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V3D_PERFCNT_L2T_TMUCFG_MISSES,
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V3D_PERFCNT_L2T_SLC0_MISSES,
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V3D_PERFCNT_L2T_SLC1_MISSES,
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V3D_PERFCNT_L2T_SLC2_MISSES,
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|
V3D_PERFCNT_CORE_MEM_WRITES,
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|
V3D_PERFCNT_L2T_MEM_WRITES,
|
|
V3D_PERFCNT_PTB_MEM_WRITES,
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|
V3D_PERFCNT_TLB_MEM_WRITES,
|
|
V3D_PERFCNT_CORE_MEM_READS,
|
|
V3D_PERFCNT_L2T_MEM_READS,
|
|
V3D_PERFCNT_PTB_MEM_READS,
|
|
V3D_PERFCNT_PSE_MEM_READS,
|
|
V3D_PERFCNT_TLB_MEM_READS,
|
|
V3D_PERFCNT_GMP_MEM_READS,
|
|
V3D_PERFCNT_PTB_W_MEM_WORDS,
|
|
V3D_PERFCNT_TLB_W_MEM_WORDS,
|
|
V3D_PERFCNT_PSE_R_MEM_WORDS,
|
|
V3D_PERFCNT_TLB_R_MEM_WORDS,
|
|
V3D_PERFCNT_TMU_MRU_HITS,
|
|
V3D_PERFCNT_COMPUTE_ACTIVE,
|
|
V3D_PERFCNT_NUM,
|
|
};
|
|
|
|
#define DRM_V3D_MAX_PERF_COUNTERS 32
|
|
|
|
struct drm_v3d_perfmon_create {
|
|
__u32 id;
|
|
__u32 ncounters;
|
|
__u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
|
|
};
|
|
|
|
struct drm_v3d_perfmon_destroy {
|
|
__u32 id;
|
|
};
|
|
|
|
/*
|
|
* Returns the values of the performance counters tracked by this
|
|
* perfmon (as an array of ncounters u64 values).
|
|
*
|
|
* No implicit synchronization is performed, so the user has to
|
|
* guarantee that any jobs using this perfmon have already been
|
|
* completed (probably by blocking on the seqno returned by the
|
|
* last exec that used the perfmon).
|
|
*/
|
|
struct drm_v3d_perfmon_get_values {
|
|
__u32 id;
|
|
__u32 pad;
|
|
__u64 values_ptr;
|
|
};
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* _V3D_DRM_H_ */
|