169 lines
3.5 KiB
C
169 lines
3.5 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2018 Intel Corporation
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*/
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#include "igt_gem_utils.h"
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#include "gem/i915_gem_context.h"
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#include "gem/i915_gem_pm.h"
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#include "gt/intel_context.h"
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#include "gt/intel_gt.h"
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#include "i915_vma.h"
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#include "i915_drv.h"
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#include "i915_request.h"
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struct i915_request *
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igt_request_alloc(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
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{
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struct intel_context *ce;
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struct i915_request *rq;
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/*
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* Pinning the contexts may generate requests in order to acquire
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* GGTT space, so do this first before we reserve a seqno for
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* ourselves.
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*/
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ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
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if (IS_ERR(ce))
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return ERR_CAST(ce);
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rq = intel_context_create_request(ce);
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intel_context_put(ce);
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return rq;
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}
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struct i915_vma *
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igt_emit_store_dw(struct i915_vma *vma,
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u64 offset,
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unsigned long count,
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u32 val)
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{
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struct drm_i915_gem_object *obj;
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const int gen = INTEL_GEN(vma->vm->i915);
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unsigned long n, size;
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u32 *cmd;
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int err;
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size = (4 * count + 1) * sizeof(u32);
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size = round_up(size, PAGE_SIZE);
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obj = i915_gem_object_create_internal(vma->vm->i915, size);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
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if (IS_ERR(cmd)) {
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err = PTR_ERR(cmd);
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goto err;
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}
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GEM_BUG_ON(offset + (count - 1) * PAGE_SIZE > vma->node.size);
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offset += vma->node.start;
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for (n = 0; n < count; n++) {
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if (gen >= 8) {
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*cmd++ = MI_STORE_DWORD_IMM_GEN4;
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*cmd++ = lower_32_bits(offset);
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*cmd++ = upper_32_bits(offset);
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*cmd++ = val;
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} else if (gen >= 4) {
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*cmd++ = MI_STORE_DWORD_IMM_GEN4 |
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(gen < 6 ? MI_USE_GGTT : 0);
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*cmd++ = 0;
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*cmd++ = offset;
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*cmd++ = val;
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} else {
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*cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
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*cmd++ = offset;
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*cmd++ = val;
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}
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offset += PAGE_SIZE;
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}
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*cmd = MI_BATCH_BUFFER_END;
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i915_gem_object_unpin_map(obj);
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intel_gt_chipset_flush(vma->vm->gt);
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vma = i915_vma_instance(obj, vma->vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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goto err;
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return vma;
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err:
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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int igt_gpu_fill_dw(struct intel_context *ce,
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struct i915_vma *vma, u64 offset,
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unsigned long count, u32 val)
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{
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struct i915_request *rq;
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struct i915_vma *batch;
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unsigned int flags;
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int err;
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GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
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GEM_BUG_ON(!i915_vma_is_pinned(vma));
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batch = igt_emit_store_dw(vma, offset, count, val);
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if (IS_ERR(batch))
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return PTR_ERR(batch);
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto err_batch;
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}
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flags = 0;
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if (INTEL_GEN(ce->vm->i915) <= 5)
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flags |= I915_DISPATCH_SECURE;
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err = rq->engine->emit_bb_start(rq,
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batch->node.start, batch->node.size,
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flags);
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if (err)
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goto err_request;
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i915_vma_lock(batch);
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err = i915_request_await_object(rq, batch->obj, false);
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if (err == 0)
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err = i915_vma_move_to_active(batch, rq, 0);
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i915_vma_unlock(batch);
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if (err)
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goto skip_request;
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i915_vma_lock(vma);
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err = i915_request_await_object(rq, vma->obj, true);
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if (err == 0)
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err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
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i915_vma_unlock(vma);
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if (err)
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goto skip_request;
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i915_request_add(rq);
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i915_vma_unpin_and_release(&batch, 0);
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return 0;
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skip_request:
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i915_request_skip(rq, err);
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err_request:
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i915_request_add(rq);
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err_batch:
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i915_vma_unpin_and_release(&batch, 0);
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return err;
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}
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