143 lines
3.1 KiB
Plaintext
143 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* Freescale Media5200 board Device Tree Source
|
|
*
|
|
* Copyright 2009 Secret Lab Technologies Ltd.
|
|
* Grant Likely <grant.likely@secretlab.ca>
|
|
* Steven Cavanagh <scavanagh@secretlab.ca>
|
|
*/
|
|
|
|
/include/ "mpc5200b.dtsi"
|
|
|
|
&gpt0 { fsl,has-wdt; };
|
|
|
|
/ {
|
|
model = "fsl,media5200";
|
|
compatible = "fsl,media5200";
|
|
|
|
aliases {
|
|
console = &console;
|
|
ethernet0 = ð0;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = &console;
|
|
};
|
|
|
|
cpus {
|
|
PowerPC,5200@0 {
|
|
timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
|
|
bus-frequency = <132000000>; // 132 MHz
|
|
clock-frequency = <396000000>; // 396 MHz
|
|
};
|
|
};
|
|
|
|
memory {
|
|
reg = <0x00000000 0x08000000>; // 128MB RAM
|
|
};
|
|
|
|
soc5200@f0000000 {
|
|
bus-frequency = <132000000>;// 132 MHz
|
|
|
|
psc@2000 { // PSC1
|
|
status = "disabled";
|
|
};
|
|
|
|
psc@2200 { // PSC2
|
|
status = "disabled";
|
|
};
|
|
|
|
psc@2400 { // PSC3
|
|
status = "disabled";
|
|
};
|
|
|
|
psc@2600 { // PSC4
|
|
status = "disabled";
|
|
};
|
|
|
|
psc@2800 { // PSC5
|
|
status = "disabled";
|
|
};
|
|
|
|
// PSC6 in uart mode
|
|
console: psc@2c00 { // PSC6
|
|
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
|
};
|
|
|
|
ethernet@3000 {
|
|
phy-handle = <&phy0>;
|
|
};
|
|
|
|
mdio@3000 {
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
usb@1000 {
|
|
reg = <0x1000 0x100>;
|
|
};
|
|
};
|
|
|
|
pci@f0000d00 {
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
|
|
0xc000 0 0 2 &media5200_fpga 0 3
|
|
0xc000 0 0 3 &media5200_fpga 0 4
|
|
0xc000 0 0 4 &media5200_fpga 0 5
|
|
|
|
0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
|
|
0xc800 0 0 2 &media5200_fpga 0 4
|
|
0xc800 0 0 3 &media5200_fpga 0 5
|
|
0xc800 0 0 4 &media5200_fpga 0 2
|
|
|
|
0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
|
|
0xd000 0 0 2 &media5200_fpga 0 5
|
|
|
|
0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
|
|
>;
|
|
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
|
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
|
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
|
interrupt-parent = <&mpc5200_pic>;
|
|
};
|
|
|
|
localbus {
|
|
ranges = < 0 0 0xfc000000 0x02000000
|
|
1 0 0xfe000000 0x02000000
|
|
2 0 0xf0010000 0x00010000
|
|
3 0 0xf0020000 0x00010000 >;
|
|
flash@0,0 {
|
|
compatible = "amd,am29lv28ml", "cfi-flash";
|
|
reg = <0 0x0 0x2000000>; // 32 MB
|
|
bank-width = <4>; // Width in bytes of the flash bank
|
|
device-width = <2>; // Two devices on each bank
|
|
};
|
|
|
|
flash@1,0 {
|
|
compatible = "amd,am29lv28ml", "cfi-flash";
|
|
reg = <1 0 0x2000000>; // 32 MB
|
|
bank-width = <4>; // Width in bytes of the flash bank
|
|
device-width = <2>; // Two devices on each bank
|
|
};
|
|
|
|
media5200_fpga: fpga@2,0 {
|
|
compatible = "fsl,media5200-fpga";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>; // 0:bank 1:id; no type field
|
|
reg = <2 0 0x10000>;
|
|
|
|
interrupt-parent = <&mpc5200_pic>;
|
|
interrupts = <0 0 3 // IRQ bank 0
|
|
1 1 3>; // IRQ bank 1
|
|
};
|
|
|
|
uart@3,0 {
|
|
compatible = "ti,tl16c752bpt";
|
|
reg = <3 0 0x10000>;
|
|
interrupt-parent = <&media5200_fpga>;
|
|
interrupts = <0 0 0 1>; // 2 irqs
|
|
};
|
|
};
|
|
};
|