560 lines
13 KiB
Plaintext
560 lines
13 KiB
Plaintext
/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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#include <dt-bindings/reset/qcom,gcc-msm8960.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm APQ8064";
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compatible = "qcom,apq8064";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@2 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@3 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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cpu-idle-states = <&CPU_SPC>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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idle-states {
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CPU_SPC: spc {
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compatible = "qcom,idle-state-spc",
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"arm,idle-state";
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entry-latency-us = <400>;
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exit-latency-us = <900>;
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min-residency-us = <3000>;
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};
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 10 0x304>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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tlmm_pinmux: pinctrl@800000 {
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compatible = "qcom,apq8064-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&ps_hold>;
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sdc4_gpios: sdc4-gpios {
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pios {
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pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
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function = "sdc4";
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};
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};
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ps_hold: ps_hold {
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mux {
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pins = "gpio78";
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function = "ps_hold";
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};
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};
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i2c1_pins: i2c1 {
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mux {
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pins = "gpio20", "gpio21";
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function = "gsbi1";
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};
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};
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i2c3_pins: i2c3 {
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mux {
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pins = "gpio8", "gpio9";
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function = "gsbi3";
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};
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};
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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};
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timer@200a000 {
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x80000>;
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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acc2: clock-controller@20a8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
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};
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acc3: clock-controller@20b8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
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};
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saw0: power-controller@2089000 {
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compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw1: power-controller@2099000 {
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compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw2: power-controller@20a9000 {
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compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
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reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw3: power-controller@20b9000 {
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compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
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reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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gsbi1: gsbi@12440000 {
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status = "disabled";
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <1>;
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reg = <0x12440000 0x100>;
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clocks = <&gcc GSBI1_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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i2c1: i2c@12460000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x12460000 0x1000>;
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interrupts = <0 194 IRQ_TYPE_NONE>;
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clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gsbi2: gsbi@12480000 {
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status = "disabled";
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <2>;
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reg = <0x12480000 0x100>;
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clocks = <&gcc GSBI2_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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i2c2: i2c@124a0000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x124a0000 0x1000>;
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interrupts = <0 196 IRQ_TYPE_NONE>;
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clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gsbi3: gsbi@16200000 {
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status = "disabled";
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x16200000 0x100>;
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clocks = <&gcc GSBI3_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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i2c3: i2c@16280000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16280000 0x1000>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
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clocks = <&gcc GSBI3_QUP_CLK>,
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<&gcc GSBI3_H_CLK>;
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clock-names = "core", "iface";
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};
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};
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gsbi7: gsbi@16600000 {
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status = "disabled";
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <7>;
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reg = <0x16600000 0x100>;
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clocks = <&gcc GSBI7_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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gsbi7_serial: serial@16640000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16640000 0x1000>,
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<0x16600000 0x1000>;
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interrupts = <0 158 0x0>;
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clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x00500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-apq8064";
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reg = <0x00900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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lcc: clock-controller@28000000 {
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compatible = "qcom,lcc-apq8064";
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reg = <0x28000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mmcc: clock-controller@4000000 {
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compatible = "qcom,mmcc-apq8064";
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reg = <0x4000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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l2cc: clock-controller@2011000 {
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compatible = "syscon";
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reg = <0x2011000 0x1000>;
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};
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rpm@108000 {
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compatible = "qcom,rpm-apq8064";
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reg = <0x108000 0x1000>;
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qcom,ipc = <&l2cc 0x8 2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ack", "err", "wakeup";
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regulators {
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compatible = "qcom,rpm-pm8921-regulators";
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pm8921_hdmi_switch: hdmi-switch {
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bias-pull-down;
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};
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};
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};
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usb1_phy: phy@12500000 {
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compatible = "qcom,usb-otg-ci";
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reg = <0x12500000 0x400>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
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status = "disabled";
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dr_mode = "host";
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clocks = <&gcc USB_HS1_XCVR_CLK>,
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<&gcc USB_HS1_H_CLK>;
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clock-names = "core", "iface";
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resets = <&gcc USB_HS1_RESET>;
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reset-names = "link";
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};
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usb3_phy: phy@12520000 {
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compatible = "qcom,usb-otg-ci";
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reg = <0x12520000 0x400>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
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status = "disabled";
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dr_mode = "host";
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clocks = <&gcc USB_HS3_XCVR_CLK>,
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<&gcc USB_HS3_H_CLK>;
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clock-names = "core", "iface";
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resets = <&gcc USB_HS3_RESET>;
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reset-names = "link";
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};
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usb4_phy: phy@12530000 {
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compatible = "qcom,usb-otg-ci";
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reg = <0x12530000 0x400>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
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status = "disabled";
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dr_mode = "host";
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clocks = <&gcc USB_HS4_XCVR_CLK>,
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<&gcc USB_HS4_H_CLK>;
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clock-names = "core", "iface";
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resets = <&gcc USB_HS4_RESET>;
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reset-names = "link";
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};
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gadget1: gadget@12500000 {
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compatible = "qcom,ci-hdrc";
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reg = <0x12500000 0x400>;
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status = "disabled";
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dr_mode = "peripheral";
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interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
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usb-phy = <&usb1_phy>;
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};
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usb1: usb@12500000 {
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compatible = "qcom,ehci-host";
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reg = <0x12500000 0x400>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
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status = "disabled";
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usb-phy = <&usb1_phy>;
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};
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usb3: usb@12520000 {
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compatible = "qcom,ehci-host";
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reg = <0x12520000 0x400>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
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status = "disabled";
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usb-phy = <&usb3_phy>;
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};
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usb4: usb@12530000 {
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compatible = "qcom,ehci-host";
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reg = <0x12530000 0x400>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
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status = "disabled";
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usb-phy = <&usb4_phy>;
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};
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sata_phy0: phy@1b400000 {
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compatible = "qcom,apq8064-sata-phy";
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status = "disabled";
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reg = <0x1b400000 0x200>;
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reg-names = "phy_mem";
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clocks = <&gcc SATA_PHY_CFG_CLK>;
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clock-names = "cfg";
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#phy-cells = <0>;
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};
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sata0: sata@29000000 {
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compatible = "generic-ahci";
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status = "disabled";
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reg = <0x29000000 0x180>;
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interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
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clocks = <&gcc SFAB_SATA_S_H_CLK>,
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<&gcc SATA_H_CLK>,
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<&gcc SATA_A_CLK>,
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<&gcc SATA_RXOOB_CLK>,
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<&gcc SATA_PMALIVE_CLK>;
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clock-names = "slave_iface",
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"iface",
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"bus",
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"rxoob",
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"core_pmalive";
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assigned-clocks = <&gcc SATA_RXOOB_CLK>,
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<&gcc SATA_PMALIVE_CLK>;
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assigned-clock-rates = <100000000>, <100000000>;
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phys = <&sata_phy0>;
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phy-names = "sata-phy";
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};
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/* Temporary fixed regulator */
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <2700000>;
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regulator-always-on;
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};
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sdcc1bam:dma@12402000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12402000 0x8000>;
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interrupts = <0 98 0>;
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clocks = <&gcc SDC1_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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sdcc3bam:dma@12182000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12182000 0x8000>;
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interrupts = <0 96 0>;
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clocks = <&gcc SDC3_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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sdcc4bam:dma@121c2000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x121c2000 0x8000>;
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interrupts = <0 95 0>;
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clocks = <&gcc SDC4_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdcc1: sdcc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12400000 0x2000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <96000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
sdcc3: sdcc@12180000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x12180000 0x2000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cmd_irq";
|
|
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <192000000>;
|
|
no-1-8-v;
|
|
vmmc-supply = <&vsdcc_fixed>;
|
|
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
sdcc4: sdcc@121c0000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x121c0000 0x2000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cmd_irq";
|
|
clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <48000000>;
|
|
vmmc-supply = <&vsdcc_fixed>;
|
|
vqmmc-supply = <&vsdcc_fixed>;
|
|
dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdc4_gpios>;
|
|
};
|
|
};
|
|
|
|
tcsr: syscon@1a400000 {
|
|
compatible = "qcom,tcsr-apq8064", "syscon";
|
|
reg = <0x1a400000 0x100>;
|
|
};
|
|
};
|
|
};
|