55 lines
2.0 KiB
C
55 lines
2.0 KiB
C
/*
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* clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
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* Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
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*
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* Aleksandr Frid <afrid@nvidia.com>
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* Paul Walmsley <pwalmsley@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/types.h>
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/**
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* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
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* @opp_dev: struct device * that holds the OPP table for the DFLL
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* @min_millivolts: minimum voltage (in mV) that the DFLL can operate
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* @tune0_low: DFLL tuning register 0 (low voltage range)
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* @tune0_high: DFLL tuning register 0 (high voltage range)
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* @tune1: DFLL tuning register 1
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* @assert_dvco_reset: fn ptr to place the DVCO in reset
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* @deassert_dvco_reset: fn ptr to release the DVCO reset
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* @set_clock_trimmers_high: fn ptr to tune clock trimmers for high voltage
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* @set_clock_trimmers_low: fn ptr to tune clock trimmers for low voltage
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*/
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struct tegra_dfll_soc_data {
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struct device *dev;
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unsigned int min_millivolts;
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u32 tune0_low;
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u32 tune0_high;
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u32 tune1;
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void (*init_clock_trimmers)(void);
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void (*set_clock_trimmers_high)(void);
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void (*set_clock_trimmers_low)(void);
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};
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int tegra_dfll_register(struct platform_device *pdev,
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struct tegra_dfll_soc_data *soc);
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int tegra_dfll_unregister(struct platform_device *pdev);
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int tegra_dfll_runtime_suspend(struct device *dev);
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int tegra_dfll_runtime_resume(struct device *dev);
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#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */
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