422 lines
9.4 KiB
C
422 lines
9.4 KiB
C
/*
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* IBM Automatic Server Restart driver.
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*
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* Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
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*
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* Based on driver written by Pete Reynolds.
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* Copyright (c) IBM Corporation, 1998-2004.
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*
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* This software may be used and distributed according to the terms
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* of the GNU Public License, incorporated herein by reference.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/fs.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/timer.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/dmi.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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enum {
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ASMTYPE_UNKNOWN,
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ASMTYPE_TOPAZ,
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ASMTYPE_JASPER,
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ASMTYPE_PEARL,
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ASMTYPE_JUNIPER,
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ASMTYPE_SPRUCE,
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};
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#define TOPAZ_ASR_REG_OFFSET 4
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#define TOPAZ_ASR_TOGGLE 0x40
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#define TOPAZ_ASR_DISABLE 0x80
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/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
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#define PEARL_BASE 0xe04
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#define PEARL_WRITE 0xe06
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#define PEARL_READ 0xe07
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#define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
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#define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
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/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
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#define JASPER_ASR_REG_OFFSET 0x38
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#define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
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#define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
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#define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
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#define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
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#define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
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#define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */
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#define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */
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#define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */
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static bool nowayout = WATCHDOG_NOWAYOUT;
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static unsigned long asr_is_open;
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static char asr_expect_close;
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static unsigned int asr_type, asr_base, asr_length;
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static unsigned int asr_read_addr, asr_write_addr;
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static unsigned char asr_toggle_mask, asr_disable_mask;
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static DEFINE_SPINLOCK(asr_lock);
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static void __asr_toggle(void)
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{
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unsigned char reg;
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reg = inb(asr_read_addr);
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outb(reg & ~asr_toggle_mask, asr_write_addr);
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reg = inb(asr_read_addr);
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outb(reg | asr_toggle_mask, asr_write_addr);
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reg = inb(asr_read_addr);
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outb(reg & ~asr_toggle_mask, asr_write_addr);
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reg = inb(asr_read_addr);
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}
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static void asr_toggle(void)
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{
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spin_lock(&asr_lock);
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__asr_toggle();
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spin_unlock(&asr_lock);
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}
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static void asr_enable(void)
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{
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unsigned char reg;
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spin_lock(&asr_lock);
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if (asr_type == ASMTYPE_TOPAZ) {
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/* asr_write_addr == asr_read_addr */
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reg = inb(asr_read_addr);
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outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
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asr_read_addr);
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} else {
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/*
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* First make sure the hardware timer is reset by toggling
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* ASR hardware timer line.
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*/
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__asr_toggle();
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reg = inb(asr_read_addr);
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outb(reg & ~asr_disable_mask, asr_write_addr);
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}
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reg = inb(asr_read_addr);
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spin_unlock(&asr_lock);
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}
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static void asr_disable(void)
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{
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unsigned char reg;
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spin_lock(&asr_lock);
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reg = inb(asr_read_addr);
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if (asr_type == ASMTYPE_TOPAZ)
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/* asr_write_addr == asr_read_addr */
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outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
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asr_read_addr);
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else {
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outb(reg | asr_toggle_mask, asr_write_addr);
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reg = inb(asr_read_addr);
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outb(reg | asr_disable_mask, asr_write_addr);
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}
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reg = inb(asr_read_addr);
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spin_unlock(&asr_lock);
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}
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static int __init asr_get_base_address(void)
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{
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unsigned char low, high;
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const char *type = "";
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asr_length = 1;
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switch (asr_type) {
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case ASMTYPE_TOPAZ:
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/* SELECT SuperIO CHIP FOR QUERYING
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(WRITE 0x07 TO BOTH 0x2E and 0x2F) */
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outb(0x07, 0x2e);
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outb(0x07, 0x2f);
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/* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
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outb(0x60, 0x2e);
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high = inb(0x2f);
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/* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
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outb(0x61, 0x2e);
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low = inb(0x2f);
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asr_base = (high << 16) | low;
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asr_read_addr = asr_write_addr =
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asr_base + TOPAZ_ASR_REG_OFFSET;
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asr_length = 5;
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break;
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case ASMTYPE_JASPER:
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type = "Jaspers ";
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#if 0
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u32 r;
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/* Suggested fix */
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pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
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if (pdev == NULL)
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return -ENODEV;
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pci_read_config_dword(pdev, 0x58, &r);
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asr_base = r & 0xFFFE;
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pci_dev_put(pdev);
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#else
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/* FIXME: need to use pci_config_lock here,
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but it's not exported */
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/* spin_lock_irqsave(&pci_config_lock, flags);*/
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/* Select the SuperIO chip in the PCI I/O port register */
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outl(0x8000f858, 0xcf8);
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/* BUS 0, Slot 1F, fnc 0, offset 58 */
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/*
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* Read the base address for the SuperIO chip.
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* Only the lower 16 bits are valid, but the address is word
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* aligned so the last bit must be masked off.
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*/
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asr_base = inl(0xcfc) & 0xfffe;
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/* spin_unlock_irqrestore(&pci_config_lock, flags);*/
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#endif
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asr_read_addr = asr_write_addr =
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asr_base + JASPER_ASR_REG_OFFSET;
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asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
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asr_disable_mask = JASPER_ASR_DISABLE_MASK;
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asr_length = JASPER_ASR_REG_OFFSET + 1;
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break;
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case ASMTYPE_PEARL:
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type = "Pearls ";
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asr_base = PEARL_BASE;
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asr_read_addr = PEARL_READ;
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asr_write_addr = PEARL_WRITE;
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asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
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asr_disable_mask = PEARL_ASR_DISABLE_MASK;
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asr_length = 4;
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break;
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case ASMTYPE_JUNIPER:
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type = "Junipers ";
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asr_base = JUNIPER_BASE_ADDRESS;
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asr_read_addr = asr_write_addr = asr_base;
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asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
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asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
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break;
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case ASMTYPE_SPRUCE:
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type = "Spruce's ";
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asr_base = SPRUCE_BASE_ADDRESS;
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asr_read_addr = asr_write_addr = asr_base;
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asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
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asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
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break;
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}
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if (!request_region(asr_base, asr_length, "ibmasr")) {
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pr_err("address %#x already in use\n", asr_base);
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return -EBUSY;
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}
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pr_info("found %sASR @ addr %#x\n", type, asr_base);
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return 0;
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}
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static ssize_t asr_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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if (count) {
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if (!nowayout) {
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size_t i;
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/* In case it was set long ago */
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asr_expect_close = 0;
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for (i = 0; i != count; i++) {
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char c;
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if (get_user(c, buf + i))
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return -EFAULT;
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if (c == 'V')
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asr_expect_close = 42;
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}
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}
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asr_toggle();
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}
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return count;
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}
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static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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{
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static const struct watchdog_info ident = {
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.options = WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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.identity = "IBM ASR",
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};
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void __user *argp = (void __user *)arg;
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int __user *p = argp;
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int heartbeat;
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
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case WDIOC_GETSTATUS:
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case WDIOC_GETBOOTSTATUS:
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return put_user(0, p);
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case WDIOC_SETOPTIONS:
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{
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int new_options, retval = -EINVAL;
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if (get_user(new_options, p))
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return -EFAULT;
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if (new_options & WDIOS_DISABLECARD) {
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asr_disable();
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retval = 0;
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}
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if (new_options & WDIOS_ENABLECARD) {
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asr_enable();
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asr_toggle();
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retval = 0;
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}
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return retval;
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}
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case WDIOC_KEEPALIVE:
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asr_toggle();
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return 0;
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/*
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* The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
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* and WDIOC_GETTIMEOUT always returns 256.
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*/
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case WDIOC_GETTIMEOUT:
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heartbeat = 256;
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return put_user(heartbeat, p);
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default:
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return -ENOTTY;
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}
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}
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static int asr_open(struct inode *inode, struct file *file)
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{
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if (test_and_set_bit(0, &asr_is_open))
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return -EBUSY;
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asr_toggle();
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asr_enable();
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return stream_open(inode, file);
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}
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static int asr_release(struct inode *inode, struct file *file)
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{
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if (asr_expect_close == 42)
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asr_disable();
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else {
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pr_crit("unexpected close, not stopping watchdog!\n");
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asr_toggle();
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}
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clear_bit(0, &asr_is_open);
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asr_expect_close = 0;
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return 0;
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}
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static const struct file_operations asr_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = asr_write,
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.unlocked_ioctl = asr_ioctl,
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.open = asr_open,
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.release = asr_release,
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};
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static struct miscdevice asr_miscdev = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &asr_fops,
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};
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struct ibmasr_id {
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const char *desc;
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int type;
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};
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static struct ibmasr_id ibmasr_id_table[] __initdata = {
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{ "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
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{ "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
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{ "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
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{ "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
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{ "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
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{ NULL }
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};
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static int __init ibmasr_init(void)
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{
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struct ibmasr_id *id;
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int rc;
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for (id = ibmasr_id_table; id->desc; id++) {
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if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
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asr_type = id->type;
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break;
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}
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}
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if (!asr_type)
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return -ENODEV;
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rc = asr_get_base_address();
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if (rc)
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return rc;
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rc = misc_register(&asr_miscdev);
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if (rc < 0) {
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release_region(asr_base, asr_length);
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pr_err("failed to register misc device\n");
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return rc;
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}
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return 0;
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}
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static void __exit ibmasr_exit(void)
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{
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if (!nowayout)
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asr_disable();
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misc_deregister(&asr_miscdev);
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release_region(asr_base, asr_length);
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}
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module_init(ibmasr_init);
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module_exit(ibmasr_exit);
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
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MODULE_AUTHOR("Andrey Panin");
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MODULE_LICENSE("GPL");
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