204 lines
5.9 KiB
C
204 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SDHCI_PCI_H
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#define __SDHCI_PCI_H
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/*
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* PCI device IDs, sub IDs
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*/
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#define PCI_DEVICE_ID_O2_SDS0 0x8420
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#define PCI_DEVICE_ID_O2_SDS1 0x8421
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#define PCI_DEVICE_ID_O2_FUJIN2 0x8520
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#define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
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#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
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#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
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#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
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#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
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#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
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#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
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#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
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#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
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#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
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#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
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#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
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#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
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#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
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#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
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#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
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#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
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#define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db
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#define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
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#define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
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#define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
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#define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
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#define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
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#define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
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#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
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#define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
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#define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
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#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
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#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
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#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
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#define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4
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#define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5
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#define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
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#define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4
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#define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8
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#define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b47
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#define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48
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#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4
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#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5
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#define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5
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#define PCI_DEVICE_ID_INTEL_JSL_EMMC 0x4dc4
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#define PCI_DEVICE_ID_INTEL_JSL_SD 0x4df8
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#define PCI_DEVICE_ID_INTEL_LKF_EMMC 0x98c4
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#define PCI_DEVICE_ID_INTEL_LKF_SD 0x98f8
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#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
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#define PCI_DEVICE_ID_VIA_95D0 0x95d0
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#define PCI_DEVICE_ID_REALTEK_5250 0x5250
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#define PCI_SUBDEVICE_ID_NI_7884 0x7884
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#define PCI_SUBDEVICE_ID_NI_78E3 0x78e3
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#define PCI_VENDOR_ID_ARASAN 0x16e6
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#define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670
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#define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202
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#define PCI_DEVICE_ID_GLI_9755 0x9755
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#define PCI_DEVICE_ID_GLI_9750 0x9750
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#define PCI_DEVICE_ID_GLI_9763E 0xe763
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/*
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* PCI device class and mask
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*/
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#define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8)
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#define PCI_CLASS_MASK 0xFFFF00
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/*
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* Macros for PCI device-description
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*/
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#define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
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#define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
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#define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
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#define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
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.vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
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.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
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.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
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}
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#define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
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.vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
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.subvendor = _PCI_VEND(subvend), \
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.subdevice = _PCI_SUBDEV(subvend, subdev), \
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.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
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}
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#define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
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.vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
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.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
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.class = (cl), .class_mask = (cl_msk), \
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.driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
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}
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/*
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* PCI registers
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*/
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#define PCI_SDHCI_IFPIO 0x00
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#define PCI_SDHCI_IFDMA 0x01
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#define PCI_SDHCI_IFVENDOR 0x02
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#define PCI_SLOT_INFO 0x40 /* 8 bits */
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#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
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#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
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#define MAX_SLOTS 8
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struct sdhci_pci_chip;
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struct sdhci_pci_slot;
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struct sdhci_pci_fixes {
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unsigned int quirks;
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unsigned int quirks2;
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bool allow_runtime_pm;
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bool own_cd_for_runtime_pm;
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int (*probe) (struct sdhci_pci_chip *);
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int (*probe_slot) (struct sdhci_pci_slot *);
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int (*add_host) (struct sdhci_pci_slot *);
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void (*remove_slot) (struct sdhci_pci_slot *, int);
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#ifdef CONFIG_PM_SLEEP
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int (*suspend) (struct sdhci_pci_chip *);
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int (*resume) (struct sdhci_pci_chip *);
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#endif
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#ifdef CONFIG_PM
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int (*runtime_suspend) (struct sdhci_pci_chip *);
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int (*runtime_resume) (struct sdhci_pci_chip *);
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#endif
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const struct sdhci_ops *ops;
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size_t priv_size;
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};
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struct sdhci_pci_slot {
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struct sdhci_pci_chip *chip;
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struct sdhci_host *host;
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struct sdhci_pci_data *data;
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int rst_n_gpio;
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int cd_gpio;
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int cd_irq;
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int cd_idx;
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bool cd_override_level;
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void (*hw_reset)(struct sdhci_host *host);
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unsigned long private[] ____cacheline_aligned;
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};
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struct sdhci_pci_chip {
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struct pci_dev *pdev;
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unsigned int quirks;
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unsigned int quirks2;
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bool allow_runtime_pm;
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bool pm_retune;
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bool rpm_retune;
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const struct sdhci_pci_fixes *fixes;
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int num_slots; /* Slots on controller */
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struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
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};
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static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
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{
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return (void *)slot->private;
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}
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#ifdef CONFIG_PM_SLEEP
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int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
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#endif
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int sdhci_pci_enable_dma(struct sdhci_host *host);
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extern const struct sdhci_pci_fixes sdhci_arasan;
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extern const struct sdhci_pci_fixes sdhci_snps;
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extern const struct sdhci_pci_fixes sdhci_o2;
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extern const struct sdhci_pci_fixes sdhci_gl9750;
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extern const struct sdhci_pci_fixes sdhci_gl9755;
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extern const struct sdhci_pci_fixes sdhci_gl9763e;
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#endif /* __SDHCI_PCI_H */
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