854 lines
21 KiB
C
854 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/aer.h>
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#include <linux/fs.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/idr.h>
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#include <linux/intel-svm.h>
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#include <linux/iommu.h>
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#include <uapi/linux/idxd.h>
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#include <linux/dmaengine.h>
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#include "../dmaengine.h"
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#include "registers.h"
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#include "idxd.h"
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#include "perfmon.h"
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MODULE_VERSION(IDXD_DRIVER_VERSION);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Intel Corporation");
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static bool sva = true;
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module_param(sva, bool, 0644);
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MODULE_PARM_DESC(sva, "Toggle SVA support on/off");
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#define DRV_NAME "idxd"
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bool support_enqcmd;
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DEFINE_IDA(idxd_ida);
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static struct idxd_driver_data idxd_driver_data[] = {
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[IDXD_TYPE_DSA] = {
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.name_prefix = "dsa",
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.type = IDXD_TYPE_DSA,
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.compl_size = sizeof(struct dsa_completion_record),
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.align = 32,
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.dev_type = &dsa_device_type,
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},
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[IDXD_TYPE_IAX] = {
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.name_prefix = "iax",
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.type = IDXD_TYPE_IAX,
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.compl_size = sizeof(struct iax_completion_record),
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.align = 64,
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.dev_type = &iax_device_type,
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},
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};
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static struct pci_device_id idxd_pci_tbl[] = {
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/* DSA ver 1.0 platforms */
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{ PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) },
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/* IAX ver 1.0 platforms */
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{ PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
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static int idxd_setup_interrupts(struct idxd_device *idxd)
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{
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struct pci_dev *pdev = idxd->pdev;
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struct device *dev = &pdev->dev;
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struct idxd_irq_entry *irq_entry;
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int i, msixcnt;
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int rc = 0;
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msixcnt = pci_msix_vec_count(pdev);
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if (msixcnt < 0) {
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dev_err(dev, "Not MSI-X interrupt capable.\n");
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return -ENOSPC;
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}
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rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX);
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if (rc != msixcnt) {
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dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
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return -ENOSPC;
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}
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dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
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/*
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* We implement 1 completion list per MSI-X entry except for
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* entry 0, which is for errors and others.
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*/
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idxd->irq_entries = kcalloc_node(msixcnt, sizeof(struct idxd_irq_entry),
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GFP_KERNEL, dev_to_node(dev));
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if (!idxd->irq_entries) {
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rc = -ENOMEM;
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goto err_irq_entries;
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}
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for (i = 0; i < msixcnt; i++) {
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idxd->irq_entries[i].id = i;
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idxd->irq_entries[i].idxd = idxd;
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idxd->irq_entries[i].vector = pci_irq_vector(pdev, i);
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spin_lock_init(&idxd->irq_entries[i].list_lock);
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}
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irq_entry = &idxd->irq_entries[0];
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rc = request_threaded_irq(irq_entry->vector, NULL, idxd_misc_thread,
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0, "idxd-misc", irq_entry);
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if (rc < 0) {
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dev_err(dev, "Failed to allocate misc interrupt.\n");
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goto err_misc_irq;
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}
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dev_dbg(dev, "Allocated idxd-misc handler on msix vector %d\n", irq_entry->vector);
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/* first MSI-X entry is not for wq interrupts */
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idxd->num_wq_irqs = msixcnt - 1;
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for (i = 1; i < msixcnt; i++) {
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irq_entry = &idxd->irq_entries[i];
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init_llist_head(&idxd->irq_entries[i].pending_llist);
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INIT_LIST_HEAD(&idxd->irq_entries[i].work_list);
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rc = request_threaded_irq(irq_entry->vector, NULL,
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idxd_wq_thread, 0, "idxd-portal", irq_entry);
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if (rc < 0) {
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dev_err(dev, "Failed to allocate irq %d.\n", irq_entry->vector);
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goto err_wq_irqs;
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}
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dev_dbg(dev, "Allocated idxd-msix %d for vector %d\n", i, irq_entry->vector);
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if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
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/*
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* The MSIX vector enumeration starts at 1 with vector 0 being the
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* misc interrupt that handles non I/O completion events. The
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* interrupt handles are for IMS enumeration on guest. The misc
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* interrupt vector does not require a handle and therefore we start
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* the int_handles at index 0. Since 'i' starts at 1, the first
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* int_handles index will be 0.
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*/
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rc = idxd_device_request_int_handle(idxd, i, &idxd->int_handles[i - 1],
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IDXD_IRQ_MSIX);
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if (rc < 0) {
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free_irq(irq_entry->vector, irq_entry);
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goto err_wq_irqs;
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}
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dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i - 1]);
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}
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}
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idxd_unmask_error_interrupts(idxd);
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idxd_msix_perm_setup(idxd);
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return 0;
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err_wq_irqs:
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while (--i >= 0) {
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irq_entry = &idxd->irq_entries[i];
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free_irq(irq_entry->vector, irq_entry);
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if (i != 0)
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idxd_device_release_int_handle(idxd,
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idxd->int_handles[i], IDXD_IRQ_MSIX);
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}
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err_misc_irq:
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/* Disable error interrupt generation */
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idxd_mask_error_interrupts(idxd);
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err_irq_entries:
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pci_free_irq_vectors(pdev);
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dev_err(dev, "No usable interrupts\n");
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return rc;
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}
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static void idxd_cleanup_interrupts(struct idxd_device *idxd)
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{
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struct pci_dev *pdev = idxd->pdev;
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struct idxd_irq_entry *irq_entry;
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int i, msixcnt;
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msixcnt = pci_msix_vec_count(pdev);
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if (msixcnt <= 0)
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return;
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irq_entry = &idxd->irq_entries[0];
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free_irq(irq_entry->vector, irq_entry);
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for (i = 1; i < msixcnt; i++) {
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irq_entry = &idxd->irq_entries[i];
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if (idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))
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idxd_device_release_int_handle(idxd, idxd->int_handles[i],
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IDXD_IRQ_MSIX);
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free_irq(irq_entry->vector, irq_entry);
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}
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idxd_mask_error_interrupts(idxd);
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pci_free_irq_vectors(pdev);
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}
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static int idxd_setup_wqs(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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struct idxd_wq *wq;
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int i, rc;
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idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *),
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GFP_KERNEL, dev_to_node(dev));
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if (!idxd->wqs)
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return -ENOMEM;
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for (i = 0; i < idxd->max_wqs; i++) {
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wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
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if (!wq) {
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rc = -ENOMEM;
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goto err;
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}
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wq->id = i;
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wq->idxd = idxd;
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device_initialize(&wq->conf_dev);
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wq->conf_dev.parent = &idxd->conf_dev;
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wq->conf_dev.bus = &dsa_bus_type;
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wq->conf_dev.type = &idxd_wq_device_type;
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rc = dev_set_name(&wq->conf_dev, "wq%d.%d", idxd->id, wq->id);
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if (rc < 0) {
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put_device(&wq->conf_dev);
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goto err;
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}
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mutex_init(&wq->wq_lock);
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init_waitqueue_head(&wq->err_queue);
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init_completion(&wq->wq_dead);
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wq->max_xfer_bytes = idxd->max_xfer_bytes;
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wq->max_batch_size = idxd->max_batch_size;
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wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
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if (!wq->wqcfg) {
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put_device(&wq->conf_dev);
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rc = -ENOMEM;
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goto err;
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}
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idxd->wqs[i] = wq;
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}
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return 0;
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err:
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while (--i >= 0)
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put_device(&idxd->wqs[i]->conf_dev);
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return rc;
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}
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static int idxd_setup_engines(struct idxd_device *idxd)
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{
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struct idxd_engine *engine;
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struct device *dev = &idxd->pdev->dev;
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int i, rc;
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idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *),
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GFP_KERNEL, dev_to_node(dev));
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if (!idxd->engines)
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return -ENOMEM;
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for (i = 0; i < idxd->max_engines; i++) {
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engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
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if (!engine) {
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rc = -ENOMEM;
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goto err;
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}
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engine->id = i;
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engine->idxd = idxd;
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device_initialize(&engine->conf_dev);
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engine->conf_dev.parent = &idxd->conf_dev;
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engine->conf_dev.bus = &dsa_bus_type;
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engine->conf_dev.type = &idxd_engine_device_type;
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rc = dev_set_name(&engine->conf_dev, "engine%d.%d", idxd->id, engine->id);
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if (rc < 0) {
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put_device(&engine->conf_dev);
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goto err;
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}
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idxd->engines[i] = engine;
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}
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return 0;
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err:
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while (--i >= 0)
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put_device(&idxd->engines[i]->conf_dev);
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return rc;
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}
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static int idxd_setup_groups(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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struct idxd_group *group;
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int i, rc;
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idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *),
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GFP_KERNEL, dev_to_node(dev));
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if (!idxd->groups)
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return -ENOMEM;
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for (i = 0; i < idxd->max_groups; i++) {
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group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
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if (!group) {
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rc = -ENOMEM;
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goto err;
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}
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group->id = i;
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group->idxd = idxd;
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device_initialize(&group->conf_dev);
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group->conf_dev.parent = &idxd->conf_dev;
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group->conf_dev.bus = &dsa_bus_type;
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group->conf_dev.type = &idxd_group_device_type;
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rc = dev_set_name(&group->conf_dev, "group%d.%d", idxd->id, group->id);
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if (rc < 0) {
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put_device(&group->conf_dev);
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goto err;
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}
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idxd->groups[i] = group;
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group->tc_a = -1;
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group->tc_b = -1;
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}
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return 0;
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err:
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while (--i >= 0)
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put_device(&idxd->groups[i]->conf_dev);
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return rc;
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}
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static void idxd_cleanup_internals(struct idxd_device *idxd)
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{
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int i;
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for (i = 0; i < idxd->max_groups; i++)
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put_device(&idxd->groups[i]->conf_dev);
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for (i = 0; i < idxd->max_engines; i++)
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put_device(&idxd->engines[i]->conf_dev);
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for (i = 0; i < idxd->max_wqs; i++)
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put_device(&idxd->wqs[i]->conf_dev);
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destroy_workqueue(idxd->wq);
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}
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static int idxd_setup_internals(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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int rc, i;
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init_waitqueue_head(&idxd->cmd_waitq);
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if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
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idxd->int_handles = kcalloc_node(idxd->max_wqs, sizeof(int), GFP_KERNEL,
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dev_to_node(dev));
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if (!idxd->int_handles)
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return -ENOMEM;
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}
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rc = idxd_setup_wqs(idxd);
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if (rc < 0)
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goto err_wqs;
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rc = idxd_setup_engines(idxd);
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if (rc < 0)
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goto err_engine;
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rc = idxd_setup_groups(idxd);
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if (rc < 0)
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goto err_group;
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idxd->wq = create_workqueue(dev_name(dev));
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if (!idxd->wq) {
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rc = -ENOMEM;
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goto err_wkq_create;
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}
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return 0;
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err_wkq_create:
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for (i = 0; i < idxd->max_groups; i++)
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put_device(&idxd->groups[i]->conf_dev);
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err_group:
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for (i = 0; i < idxd->max_engines; i++)
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put_device(&idxd->engines[i]->conf_dev);
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err_engine:
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for (i = 0; i < idxd->max_wqs; i++)
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put_device(&idxd->wqs[i]->conf_dev);
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err_wqs:
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kfree(idxd->int_handles);
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return rc;
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}
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static void idxd_read_table_offsets(struct idxd_device *idxd)
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{
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union offsets_reg offsets;
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struct device *dev = &idxd->pdev->dev;
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offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
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offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
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idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT;
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dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
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idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
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dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
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idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
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dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
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idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
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dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
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}
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static void idxd_read_caps(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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int i;
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/* reading generic capabilities */
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idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
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dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
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if (idxd->hw.gen_cap.cmd_cap) {
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idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
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dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
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}
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idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
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dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
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idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;
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dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
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if (idxd->hw.gen_cap.config_en)
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set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
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/* reading group capabilities */
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idxd->hw.group_cap.bits =
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ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
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dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
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idxd->max_groups = idxd->hw.group_cap.num_groups;
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dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
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idxd->max_tokens = idxd->hw.group_cap.total_tokens;
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dev_dbg(dev, "max tokens: %u\n", idxd->max_tokens);
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idxd->nr_tokens = idxd->max_tokens;
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/* read engine capabilities */
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idxd->hw.engine_cap.bits =
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ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
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dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
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idxd->max_engines = idxd->hw.engine_cap.num_engines;
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dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
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/* read workqueue capabilities */
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idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
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dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
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idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
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dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
|
|
idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
|
|
dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
|
|
idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
|
|
dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
|
|
|
|
/* reading operation capabilities */
|
|
for (i = 0; i < 4; i++) {
|
|
idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
|
|
IDXD_OPCAP_OFFSET + i * sizeof(u64));
|
|
dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
|
|
}
|
|
}
|
|
|
|
static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct idxd_device *idxd;
|
|
int rc;
|
|
|
|
idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
|
|
if (!idxd)
|
|
return NULL;
|
|
|
|
idxd->pdev = pdev;
|
|
idxd->data = data;
|
|
idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL);
|
|
if (idxd->id < 0)
|
|
return NULL;
|
|
|
|
device_initialize(&idxd->conf_dev);
|
|
idxd->conf_dev.parent = dev;
|
|
idxd->conf_dev.bus = &dsa_bus_type;
|
|
idxd->conf_dev.type = idxd->data->dev_type;
|
|
rc = dev_set_name(&idxd->conf_dev, "%s%d", idxd->data->name_prefix, idxd->id);
|
|
if (rc < 0) {
|
|
put_device(&idxd->conf_dev);
|
|
return NULL;
|
|
}
|
|
|
|
spin_lock_init(&idxd->dev_lock);
|
|
spin_lock_init(&idxd->cmd_lock);
|
|
|
|
return idxd;
|
|
}
|
|
|
|
static int idxd_enable_system_pasid(struct idxd_device *idxd)
|
|
{
|
|
int flags;
|
|
unsigned int pasid;
|
|
struct iommu_sva *sva;
|
|
|
|
flags = SVM_FLAG_SUPERVISOR_MODE;
|
|
|
|
sva = iommu_sva_bind_device(&idxd->pdev->dev, NULL, &flags);
|
|
if (IS_ERR(sva)) {
|
|
dev_warn(&idxd->pdev->dev,
|
|
"iommu sva bind failed: %ld\n", PTR_ERR(sva));
|
|
return PTR_ERR(sva);
|
|
}
|
|
|
|
pasid = iommu_sva_get_pasid(sva);
|
|
if (pasid == IOMMU_PASID_INVALID) {
|
|
iommu_sva_unbind_device(sva);
|
|
return -ENODEV;
|
|
}
|
|
|
|
idxd->sva = sva;
|
|
idxd->pasid = pasid;
|
|
dev_dbg(&idxd->pdev->dev, "system pasid: %u\n", pasid);
|
|
return 0;
|
|
}
|
|
|
|
static void idxd_disable_system_pasid(struct idxd_device *idxd)
|
|
{
|
|
|
|
iommu_sva_unbind_device(idxd->sva);
|
|
idxd->sva = NULL;
|
|
}
|
|
|
|
static int idxd_probe(struct idxd_device *idxd)
|
|
{
|
|
struct pci_dev *pdev = idxd->pdev;
|
|
struct device *dev = &pdev->dev;
|
|
int rc;
|
|
|
|
dev_dbg(dev, "%s entered and resetting device\n", __func__);
|
|
rc = idxd_device_init_reset(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
dev_dbg(dev, "IDXD reset complete\n");
|
|
|
|
if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
|
|
rc = iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA);
|
|
if (rc == 0) {
|
|
rc = idxd_enable_system_pasid(idxd);
|
|
if (rc < 0) {
|
|
iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
|
|
dev_warn(dev, "Failed to enable PASID. No SVA support: %d\n", rc);
|
|
} else {
|
|
set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
|
|
}
|
|
} else {
|
|
dev_warn(dev, "Unable to turn on SVA feature.\n");
|
|
}
|
|
} else if (!sva) {
|
|
dev_warn(dev, "User forced SVA off via module param.\n");
|
|
}
|
|
|
|
idxd_read_caps(idxd);
|
|
idxd_read_table_offsets(idxd);
|
|
|
|
rc = idxd_setup_internals(idxd);
|
|
if (rc)
|
|
goto err;
|
|
|
|
/* If the configs are readonly, then load them from device */
|
|
if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
|
|
dev_dbg(dev, "Loading RO device config\n");
|
|
rc = idxd_device_load_config(idxd);
|
|
if (rc < 0)
|
|
goto err_config;
|
|
}
|
|
|
|
rc = idxd_setup_interrupts(idxd);
|
|
if (rc)
|
|
goto err_config;
|
|
|
|
dev_dbg(dev, "IDXD interrupt setup complete.\n");
|
|
|
|
idxd->major = idxd_cdev_get_major(idxd);
|
|
|
|
rc = perfmon_pmu_init(idxd);
|
|
if (rc < 0)
|
|
dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc);
|
|
|
|
dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
|
|
return 0;
|
|
|
|
err_config:
|
|
idxd_cleanup_internals(idxd);
|
|
err:
|
|
if (device_pasid_enabled(idxd))
|
|
idxd_disable_system_pasid(idxd);
|
|
iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
|
|
return rc;
|
|
}
|
|
|
|
static void idxd_cleanup(struct idxd_device *idxd)
|
|
{
|
|
struct device *dev = &idxd->pdev->dev;
|
|
|
|
perfmon_pmu_remove(idxd);
|
|
idxd_cleanup_interrupts(idxd);
|
|
idxd_cleanup_internals(idxd);
|
|
if (device_pasid_enabled(idxd))
|
|
idxd_disable_system_pasid(idxd);
|
|
iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
|
|
}
|
|
|
|
static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct idxd_device *idxd;
|
|
struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data;
|
|
int rc;
|
|
|
|
rc = pci_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
dev_dbg(dev, "Alloc IDXD context\n");
|
|
idxd = idxd_alloc(pdev, data);
|
|
if (!idxd) {
|
|
rc = -ENOMEM;
|
|
goto err_idxd_alloc;
|
|
}
|
|
|
|
dev_dbg(dev, "Mapping BARs\n");
|
|
idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
|
|
if (!idxd->reg_base) {
|
|
rc = -ENOMEM;
|
|
goto err_iomap;
|
|
}
|
|
|
|
dev_dbg(dev, "Set DMA masks\n");
|
|
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
|
|
if (rc)
|
|
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
|
if (rc)
|
|
goto err;
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
|
|
if (rc)
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
|
if (rc)
|
|
goto err;
|
|
|
|
dev_dbg(dev, "Set PCI master\n");
|
|
pci_set_master(pdev);
|
|
pci_set_drvdata(pdev, idxd);
|
|
|
|
idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
|
|
rc = idxd_probe(idxd);
|
|
if (rc) {
|
|
dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
|
|
goto err;
|
|
}
|
|
|
|
rc = idxd_register_devices(idxd);
|
|
if (rc) {
|
|
dev_err(dev, "IDXD sysfs setup failed\n");
|
|
goto err_dev_register;
|
|
}
|
|
|
|
idxd->state = IDXD_DEV_CONF_READY;
|
|
|
|
dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
|
|
idxd->hw.version);
|
|
|
|
return 0;
|
|
|
|
err_dev_register:
|
|
idxd_cleanup(idxd);
|
|
err:
|
|
pci_iounmap(pdev, idxd->reg_base);
|
|
err_iomap:
|
|
put_device(&idxd->conf_dev);
|
|
err_idxd_alloc:
|
|
pci_disable_device(pdev);
|
|
return rc;
|
|
}
|
|
|
|
static void idxd_flush_pending_llist(struct idxd_irq_entry *ie)
|
|
{
|
|
struct idxd_desc *desc, *itr;
|
|
struct llist_node *head;
|
|
|
|
head = llist_del_all(&ie->pending_llist);
|
|
if (!head)
|
|
return;
|
|
|
|
llist_for_each_entry_safe(desc, itr, head, llnode) {
|
|
idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
|
|
idxd_free_desc(desc->wq, desc);
|
|
}
|
|
}
|
|
|
|
static void idxd_flush_work_list(struct idxd_irq_entry *ie)
|
|
{
|
|
struct idxd_desc *desc, *iter;
|
|
|
|
list_for_each_entry_safe(desc, iter, &ie->work_list, list) {
|
|
list_del(&desc->list);
|
|
idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
|
|
idxd_free_desc(desc->wq, desc);
|
|
}
|
|
}
|
|
|
|
void idxd_wqs_quiesce(struct idxd_device *idxd)
|
|
{
|
|
struct idxd_wq *wq;
|
|
int i;
|
|
|
|
for (i = 0; i < idxd->max_wqs; i++) {
|
|
wq = idxd->wqs[i];
|
|
if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL)
|
|
idxd_wq_quiesce(wq);
|
|
}
|
|
}
|
|
|
|
static void idxd_release_int_handles(struct idxd_device *idxd)
|
|
{
|
|
struct device *dev = &idxd->pdev->dev;
|
|
int i, rc;
|
|
|
|
for (i = 0; i < idxd->num_wq_irqs; i++) {
|
|
if (idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)) {
|
|
rc = idxd_device_release_int_handle(idxd, idxd->int_handles[i],
|
|
IDXD_IRQ_MSIX);
|
|
if (rc < 0)
|
|
dev_warn(dev, "irq handle %d release failed\n",
|
|
idxd->int_handles[i]);
|
|
else
|
|
dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void idxd_shutdown(struct pci_dev *pdev)
|
|
{
|
|
struct idxd_device *idxd = pci_get_drvdata(pdev);
|
|
int rc, i;
|
|
struct idxd_irq_entry *irq_entry;
|
|
int msixcnt = pci_msix_vec_count(pdev);
|
|
|
|
rc = idxd_device_disable(idxd);
|
|
if (rc)
|
|
dev_err(&pdev->dev, "Disabling device failed\n");
|
|
|
|
dev_dbg(&pdev->dev, "%s called\n", __func__);
|
|
idxd_mask_msix_vectors(idxd);
|
|
idxd_mask_error_interrupts(idxd);
|
|
|
|
for (i = 0; i < msixcnt; i++) {
|
|
irq_entry = &idxd->irq_entries[i];
|
|
synchronize_irq(irq_entry->vector);
|
|
free_irq(irq_entry->vector, irq_entry);
|
|
if (i == 0)
|
|
continue;
|
|
idxd_flush_pending_llist(irq_entry);
|
|
idxd_flush_work_list(irq_entry);
|
|
}
|
|
|
|
idxd_msix_perm_clear(idxd);
|
|
idxd_release_int_handles(idxd);
|
|
pci_free_irq_vectors(pdev);
|
|
pci_iounmap(pdev, idxd->reg_base);
|
|
pci_disable_device(pdev);
|
|
destroy_workqueue(idxd->wq);
|
|
}
|
|
|
|
static void idxd_remove(struct pci_dev *pdev)
|
|
{
|
|
struct idxd_device *idxd = pci_get_drvdata(pdev);
|
|
|
|
dev_dbg(&pdev->dev, "%s called\n", __func__);
|
|
idxd_shutdown(pdev);
|
|
if (device_pasid_enabled(idxd))
|
|
idxd_disable_system_pasid(idxd);
|
|
idxd_unregister_devices(idxd);
|
|
perfmon_pmu_remove(idxd);
|
|
iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
|
|
}
|
|
|
|
static struct pci_driver idxd_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = idxd_pci_tbl,
|
|
.probe = idxd_pci_probe,
|
|
.remove = idxd_remove,
|
|
.shutdown = idxd_shutdown,
|
|
};
|
|
|
|
static int __init idxd_init_module(void)
|
|
{
|
|
int err;
|
|
|
|
/*
|
|
* If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
|
|
* enumerating the device. We can not utilize it.
|
|
*/
|
|
if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) {
|
|
pr_warn("idxd driver failed to load without MOVDIR64B.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
|
|
pr_warn("Platform does not have ENQCMD(S) support.\n");
|
|
else
|
|
support_enqcmd = true;
|
|
|
|
perfmon_init();
|
|
|
|
err = idxd_register_bus_type();
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = idxd_register_driver();
|
|
if (err < 0)
|
|
goto err_idxd_driver_register;
|
|
|
|
err = idxd_cdev_register();
|
|
if (err)
|
|
goto err_cdev_register;
|
|
|
|
err = pci_register_driver(&idxd_pci_driver);
|
|
if (err)
|
|
goto err_pci_register;
|
|
|
|
return 0;
|
|
|
|
err_pci_register:
|
|
idxd_cdev_remove();
|
|
err_cdev_register:
|
|
idxd_unregister_driver();
|
|
err_idxd_driver_register:
|
|
idxd_unregister_bus_type();
|
|
return err;
|
|
}
|
|
module_init(idxd_init_module);
|
|
|
|
static void __exit idxd_exit_module(void)
|
|
{
|
|
idxd_unregister_driver();
|
|
pci_unregister_driver(&idxd_pci_driver);
|
|
idxd_cdev_remove();
|
|
idxd_unregister_bus_type();
|
|
perfmon_exit();
|
|
}
|
|
module_exit(idxd_exit_module);
|