52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
/*
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* Copyright (C) 2014 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_PM_CPS_H__
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#define __MIPS_ASM_PM_CPS_H__
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/*
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* The CM & CPC can only handle coherence & power control on a per-core basis,
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* thus in an MT system the VPEs within each core are coupled and can only
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* enter or exit states requiring CM or CPC assistance in unison.
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*/
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#ifdef CONFIG_MIPS_MT
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# define coupled_coherence cpu_has_mipsmt
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#else
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# define coupled_coherence 0
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#endif
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/* Enumeration of possible PM states */
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enum cps_pm_state {
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CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
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CPS_PM_CLOCK_GATED, /* Core clock gated */
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CPS_PM_POWER_GATED, /* Core power gated */
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CPS_PM_STATE_COUNT,
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};
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/**
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* cps_pm_support_state - determine whether the system supports a PM state
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* @state: the state to test for support
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*
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* Returns true if the system supports the given state, otherwise false.
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*/
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extern bool cps_pm_support_state(enum cps_pm_state state);
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/**
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* cps_pm_enter_state - enter a PM state
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* @state: the state to enter
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*
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* Enter the given PM state. If coupled_coherence is non-zero then it is
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* expected that this function be called at approximately the same time on
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* each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
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*/
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extern int cps_pm_enter_state(enum cps_pm_state state);
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#endif /* __MIPS_ASM_PM_CPS_H__ */
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