161 lines
7.3 KiB
C
161 lines
7.3 KiB
C
/*
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* lppaca.h
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* Copyright (C) 2001 Mike Corrigan IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_POWERPC_LPPACA_H
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#define _ASM_POWERPC_LPPACA_H
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#ifdef __KERNEL__
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//=============================================================================
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//
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// This control block contains the data that is shared between the
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// hypervisor (PLIC) and the OS.
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//
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//
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//----------------------------------------------------------------------------
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#include <linux/cache.h>
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#include <asm/types.h>
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#include <asm/mmu.h>
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/* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k
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* alignment is sufficient to prevent this */
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struct lppaca {
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//=============================================================================
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// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
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// NOTE: The xDynXyz fields are fields that will be dynamically changed by
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// PLIC when preparing to bring a processor online or when dispatching a
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// virtual processor!
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//=============================================================================
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u32 desc; // Eye catcher 0xD397D781 x00-x03
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u16 size; // Size of this struct x04-x05
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u16 reserved1; // Reserved x06-x07
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u16 reserved2:14; // Reserved x08-x09
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u8 shared_proc:1; // Shared processor indicator ...
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u8 secondary_thread:1; // Secondary thread indicator ...
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volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
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u8 secondary_thread_count; // Secondary thread count x0B-x0B
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volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
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volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
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u32 decr_val; // Value for Decr programming x10-x13
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u32 pmc_val; // Value for PMC regs x14-x17
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volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
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volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
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volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
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u32 dsei_data; // DSEI data x24-x27
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u64 sprg3; // SPRG3 value x28-x2F
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u8 reserved3[80]; // Reserved x30-x7F
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//=============================================================================
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// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
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//=============================================================================
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// This Dword contains a byte for each type of interrupt that can occur.
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// The IPI is a count while the others are just a binary 1 or 0.
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union {
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u64 any_int;
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struct {
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u16 reserved; // Reserved - cleared by #mpasmbl
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u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
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u8 ipi_cnt; // IPI Count
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u8 decr_int; // DECR interrupt occurred
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u8 pdc_int; // PDC interrupt occurred
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u8 quantum_int; // Interrupt quantum reached
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u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
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} fields;
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} int_dword;
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// Whenever any fields in this Dword are set then PLIC will defer the
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// processing of external interrupts. Note that PLIC will store the
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// XIRR directly into the xXirrValue field so that another XIRR will
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// not be presented until this one clears. The layout of the low
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// 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
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// entire Dword is zero or not. A non-zero value in the low order
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// 2-bytes will result in SLIC being granted the highest thread
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// priority upon return. A 0 will return to SLIC as medium priority.
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u64 plic_defer_ints_area; // Entire Dword
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// Used to pass the real SRR0/1 from PLIC to SLIC as well as to
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// pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
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u64 saved_srr0; // Saved SRR0 x10-x17
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u64 saved_srr1; // Saved SRR1 x18-x1F
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// Used to pass parms from the OS to PLIC for SetAsrAndRfid
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u64 saved_gpr3; // Saved GPR3 x20-x27
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u64 saved_gpr4; // Saved GPR4 x28-x2F
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u64 saved_gpr5; // Saved GPR5 x30-x37
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u8 reserved4; // Reserved x38-x38
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u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39
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u8 fpregs_in_use; // FP regs in use x3A-x3A
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u8 pmcregs_in_use; // PMC regs in use x3B-x3B
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volatile u32 saved_decr; // Saved Decr Value x3C-x3F
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volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
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volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
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u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
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u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
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u64 end_of_quantum; // TB at end of quantum x60-x67
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u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
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u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
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volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
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u16 slb_count; // # of SLBs to maintain x7C-x7D
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u8 idle; // Indicate OS is idle x7E
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u8 vmxregs_in_use; // VMX registers in use x7F
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//=============================================================================
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// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
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//=============================================================================
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// This is the yield_count. An "odd" value (low bit on) means that
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// the processor is yielded (either because of an OS yield or a PLIC
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// preempt). An even value implies that the processor is currently
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// executing.
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// NOTE: This value will ALWAYS be zero for dedicated processors and
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// will NEVER be zero for shared processors (ie, initialized to a 1).
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volatile u32 yield_count; // PLIC increments each dispatchx00-x03
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u32 reserved6;
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volatile u64 cmo_faults; // CMO page fault count x08-x0F
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volatile u64 cmo_fault_time; // CMO page fault time x10-x17
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u8 reserved7[104]; // Reserved x18-x7F
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//=============================================================================
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// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
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//=============================================================================
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u32 page_ins; // CMO Hint - # page ins by OS x00-x04
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u8 pmc_save_area[252]; // PMC interrupt Area x04-xFF
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} __attribute__((__aligned__(0x400)));
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extern struct lppaca lppaca[];
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/*
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* SLB shadow buffer structure as defined in the PAPR. The save_area
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* contains adjacent ESID and VSID pairs for each shadowed SLB. The
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* ESID is stored in the lower 64bits, then the VSID.
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*/
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struct slb_shadow {
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u32 persistent; // Number of persistent SLBs x00-x03
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u32 buffer_length; // Total shadow buffer length x04-x07
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u64 reserved; // Alignment x08-x0f
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struct {
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u64 esid;
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u64 vsid;
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} save_area[SLB_NUM_BOLTED]; // x10-x40
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} ____cacheline_aligned;
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extern struct slb_shadow slb_shadow[];
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_LPPACA_H */
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