156 lines
3.5 KiB
C
156 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SMP initialisation and IPI support
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* Based on arch/arm64/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/percpu.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/sched/task_stack.h>
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#include <linux/sched/mm.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/sections.h>
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#include <asm/sbi.h>
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void *__cpu_up_stack_pointer[NR_CPUS];
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void *__cpu_up_task_pointer[NR_CPUS];
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static DECLARE_COMPLETION(cpu_running);
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void __init smp_prepare_boot_cpu(void)
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{
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpuid;
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/* This covers non-smp usecase mandated by "nosmp" option */
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if (max_cpus == 0)
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return;
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for_each_possible_cpu(cpuid) {
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if (cpuid == smp_processor_id())
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continue;
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set_cpu_present(cpuid, true);
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}
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}
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void __init setup_smp(void)
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{
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struct device_node *dn;
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int hart;
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bool found_boot_cpu = false;
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int cpuid = 1;
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for_each_of_cpu_node(dn) {
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hart = riscv_of_processor_hartid(dn);
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if (hart < 0)
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continue;
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if (hart == cpuid_to_hartid_map(0)) {
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BUG_ON(found_boot_cpu);
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found_boot_cpu = 1;
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continue;
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}
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if (cpuid >= NR_CPUS) {
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pr_warn("Invalid cpuid [%d] for hartid [%d]\n",
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cpuid, hart);
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break;
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}
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cpuid_to_hartid_map(cpuid) = hart;
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cpuid++;
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}
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BUG_ON(!found_boot_cpu);
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if (cpuid > nr_cpu_ids)
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pr_warn("Total number of cpus [%d] is greater than nr_cpus option value [%d]\n",
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cpuid, nr_cpu_ids);
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for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) {
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if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID)
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set_cpu_possible(cpuid, true);
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}
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}
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int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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int ret = 0;
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int hartid = cpuid_to_hartid_map(cpu);
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tidle->thread_info.cpu = cpu;
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/*
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* On RISC-V systems, all harts boot on their own accord. Our _start
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* selects the first hart to boot the kernel and causes the remainder
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* of the harts to spin in a loop waiting for their stack pointer to be
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* setup by that main hart. Writing __cpu_up_stack_pointer signals to
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* the spinning harts that they can continue the boot process.
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*/
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smp_mb();
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WRITE_ONCE(__cpu_up_stack_pointer[hartid],
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task_stack_page(tidle) + THREAD_SIZE);
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WRITE_ONCE(__cpu_up_task_pointer[hartid], tidle);
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lockdep_assert_held(&cpu_running);
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wait_for_completion_timeout(&cpu_running,
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msecs_to_jiffies(1000));
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if (!cpu_online(cpu)) {
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pr_crit("CPU%u: failed to come online\n", cpu);
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ret = -EIO;
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}
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return ret;
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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}
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/*
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* C entry point for a secondary processor.
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*/
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asmlinkage void __init smp_callin(void)
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{
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struct mm_struct *mm = &init_mm;
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/* All kernel threads share the same mm context. */
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mmgrab(mm);
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current->active_mm = mm;
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trap_init();
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notify_cpu_starting(smp_processor_id());
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set_cpu_online(smp_processor_id(), 1);
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/*
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* Remote TLB flushes are ignored while the CPU is offline, so emit
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* a local TLB flush right now just in case.
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*/
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local_flush_tlb_all();
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complete(&cpu_running);
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/*
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* Disable preemption before enabling interrupts, so we don't try to
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* schedule a CPU that hasn't actually started yet.
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*/
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preempt_disable();
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local_irq_enable();
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cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
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}
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