72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#include <linux/gfp.h>
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#include <linux/cache.h>
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#include <linux/dma-noncoherent.h>
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#include <linux/dma-iommu.h>
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#include <asm/cacheflush.h>
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pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs)
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{
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if (!dev_is_dma_coherent(dev) || (attrs & DMA_ATTR_WRITE_COMBINE))
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return pgprot_writecombine(prot);
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return prot;
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}
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void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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__dma_map_area(phys_to_virt(paddr), size, dir);
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}
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void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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__dma_unmap_area(phys_to_virt(paddr), size, dir);
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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__dma_flush_area(page_address(page), size);
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}
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static int __init arm64_dma_init(void)
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{
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return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC));
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}
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arch_initcall(arm64_dma_init);
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#ifdef CONFIG_IOMMU_DMA
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void arch_teardown_dma_ops(struct device *dev)
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{
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dev->dma_ops = NULL;
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}
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#endif
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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int cls = cache_line_size_of_cpu();
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WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
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TAINT_CPU_OUT_OF_SPEC,
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"%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
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dev_driver_string(dev), dev_name(dev),
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ARCH_DMA_MINALIGN, cls);
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dev->dma_coherent = coherent;
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if (iommu)
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iommu_setup_dma_ops(dev, dma_base, size);
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#ifdef CONFIG_XEN
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if (xen_initial_domain())
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dev->dma_ops = xen_dma_ops;
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#endif
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}
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