Marc Zyngier 15d2bffdde KVM: arm/arm64: vgic-v3: Use PREbits to infer the number of ICH_APxRn_EL2 registers ... The GICv3 documentation is extremely confusing, as it talks about the number of priorities represented by the ICH_APxRn_EL2 registers, while it should really talk about the number of preemption levels. This leads to a bug where we may access undefined ICH_APxRn_EL2 registers, since PREbits is allowed to be smaller than PRIbits. Thankfully, nobody seem to have taken this path so far... The fix is to use ICH_VTR_EL2.PREbits instead. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Christoffer Dall <cdall@linaro.org>		2017-05-15 11:32:04 +02:00
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timer-sr.c	KVM: arm/arm64: Move cntvoff to each timer context	2017-02-08 15:13:33 +00:00
vgic-v2-sr.c	KVM: arm/arm64: vgic: Get rid of MISR and EISR fields	2017-04-09 07:49:10 -07:00
vgic-v3-sr.c	KVM: arm/arm64: vgic-v3: Use PREbits to infer the number of ICH_APxRn_EL2 registers	2017-05-15 11:32:04 +02:00