378 lines
10 KiB
C
378 lines
10 KiB
C
/*
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* drivers/ata/ahci_tegra.c
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Mikko Perttunen <mperttunen@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/ahci_platform.h>
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#include <linux/reset.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/tegra-powergate.h>
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#include <linux/regulator/consumer.h>
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#include "ahci.h"
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#define SATA_CONFIGURATION_0 0x180
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#define SATA_CONFIGURATION_EN_FPCI BIT(0)
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#define SCFG_OFFSET 0x1000
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#define T_SATA0_CFG_1 0x04
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#define T_SATA0_CFG_1_IO_SPACE BIT(0)
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#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
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#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
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#define T_SATA0_CFG_1_SERR BIT(8)
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#define T_SATA0_CFG_9 0x24
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#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
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#define SATA_FPCI_BAR5 0x94
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#define SATA_FPCI_BAR5_START_SHIFT 4
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#define SATA_INTR_MASK 0x188
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#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
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#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
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#define T_SATA0_BKDOOR_CC 0x4a4
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#define T_SATA0_CFG_SATA 0x54c
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#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
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#define T_SATA0_CFG_MISC 0x550
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#define T_SATA0_INDEX 0x680
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#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
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#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
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#define T_SATA0_CHX_PHY_CTRL2 0x69c
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#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
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#define T_SATA0_CHX_PHY_CTRL11 0x6d0
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#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
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#define FUSE_SATA_CALIB 0x124
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#define FUSE_SATA_CALIB_MASK 0x3
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struct sata_pad_calibration {
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u8 gen1_tx_amp;
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u8 gen1_tx_peak;
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u8 gen2_tx_amp;
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u8 gen2_tx_peak;
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};
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static const struct sata_pad_calibration tegra124_pad_calibration[] = {
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{0x18, 0x04, 0x18, 0x0a},
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{0x0e, 0x04, 0x14, 0x0a},
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{0x0e, 0x07, 0x1a, 0x0e},
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{0x14, 0x0e, 0x1a, 0x0e},
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};
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struct tegra_ahci_priv {
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struct platform_device *pdev;
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void __iomem *sata_regs;
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struct reset_control *sata_rst;
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struct reset_control *sata_oob_rst;
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struct reset_control *sata_cold_rst;
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/* Needs special handling, cannot use ahci_platform */
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struct clk *sata_clk;
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struct regulator_bulk_data supplies[5];
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};
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static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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int ret;
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ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
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tegra->supplies);
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if (ret)
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return ret;
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ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
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tegra->sata_clk,
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tegra->sata_rst);
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if (ret)
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goto disable_regulators;
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reset_control_assert(tegra->sata_oob_rst);
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reset_control_assert(tegra->sata_cold_rst);
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ret = ahci_platform_enable_resources(hpriv);
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if (ret)
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goto disable_power;
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reset_control_deassert(tegra->sata_cold_rst);
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reset_control_deassert(tegra->sata_oob_rst);
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return 0;
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disable_power:
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clk_disable_unprepare(tegra->sata_clk);
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tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
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disable_regulators:
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regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
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return ret;
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}
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static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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ahci_platform_disable_resources(hpriv);
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reset_control_assert(tegra->sata_rst);
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reset_control_assert(tegra->sata_oob_rst);
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reset_control_assert(tegra->sata_cold_rst);
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clk_disable_unprepare(tegra->sata_clk);
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tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
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regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
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}
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static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
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{
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struct tegra_ahci_priv *tegra = hpriv->plat_data;
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int ret;
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unsigned int val;
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struct sata_pad_calibration calib;
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ret = tegra_ahci_power_on(hpriv);
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if (ret) {
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dev_err(&tegra->pdev->dev,
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"failed to power on AHCI controller: %d\n", ret);
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return ret;
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}
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val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
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val |= SATA_CONFIGURATION_EN_FPCI;
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writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
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/* Pad calibration */
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/* FIXME Always use calibration 0. Change this to read the calibration
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* fuse once the fuse driver has landed. */
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val = 0;
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calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
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writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
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val = readl(tegra->sata_regs +
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SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
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val |= calib.gen1_tx_amp <<
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T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
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val |= calib.gen1_tx_peak <<
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T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
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writel(val, tegra->sata_regs + SCFG_OFFSET +
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T_SATA0_CHX_PHY_CTRL1_GEN1);
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val = readl(tegra->sata_regs +
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SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
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val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
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val |= calib.gen2_tx_amp <<
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T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
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val |= calib.gen2_tx_peak <<
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T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
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writel(val, tegra->sata_regs + SCFG_OFFSET +
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T_SATA0_CHX_PHY_CTRL1_GEN2);
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writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
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tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
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writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
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tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
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writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
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/* Program controller device ID */
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val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
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val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
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writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
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val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
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val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
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/* Enable IO & memory access, bus master mode */
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val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
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val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
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T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
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writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
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/* Program SATA MMIO */
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writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
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tegra->sata_regs + SATA_FPCI_BAR5);
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writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
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tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
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/* Unmask SATA interrupts */
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val = readl(tegra->sata_regs + SATA_INTR_MASK);
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val |= SATA_INTR_MASK_IP_INT_MASK;
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writel(val, tegra->sata_regs + SATA_INTR_MASK);
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return 0;
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}
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static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
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{
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tegra_ahci_power_off(hpriv);
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}
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static void tegra_ahci_host_stop(struct ata_host *host)
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{
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struct ahci_host_priv *hpriv = host->private_data;
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tegra_ahci_controller_deinit(hpriv);
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}
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static struct ata_port_operations ahci_tegra_port_ops = {
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.inherits = &ahci_ops,
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.host_stop = tegra_ahci_host_stop,
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};
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static const struct ata_port_info ahci_tegra_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_tegra_port_ops,
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};
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static const struct of_device_id tegra_ahci_of_match[] = {
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{ .compatible = "nvidia,tegra124-ahci" },
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{}
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};
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MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
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static int tegra_ahci_probe(struct platform_device *pdev)
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{
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struct ahci_host_priv *hpriv;
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struct tegra_ahci_priv *tegra;
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struct resource *res;
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int ret;
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hpriv = ahci_platform_get_resources(pdev);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
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if (!tegra)
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return -ENOMEM;
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hpriv->plat_data = tegra;
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tegra->pdev = pdev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(tegra->sata_regs))
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return PTR_ERR(tegra->sata_regs);
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tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
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if (IS_ERR(tegra->sata_rst)) {
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dev_err(&pdev->dev, "Failed to get sata reset\n");
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return PTR_ERR(tegra->sata_rst);
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}
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tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
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if (IS_ERR(tegra->sata_oob_rst)) {
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dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
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return PTR_ERR(tegra->sata_oob_rst);
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}
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tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
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if (IS_ERR(tegra->sata_cold_rst)) {
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dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
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return PTR_ERR(tegra->sata_cold_rst);
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}
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tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
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if (IS_ERR(tegra->sata_clk)) {
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dev_err(&pdev->dev, "Failed to get sata clock\n");
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return PTR_ERR(tegra->sata_clk);
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}
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tegra->supplies[0].supply = "avdd";
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tegra->supplies[1].supply = "hvdd";
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tegra->supplies[2].supply = "vddio";
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tegra->supplies[3].supply = "target-5v";
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tegra->supplies[4].supply = "target-12v";
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ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
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tegra->supplies);
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if (ret) {
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dev_err(&pdev->dev, "Failed to get regulators\n");
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return ret;
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}
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ret = tegra_ahci_controller_init(hpriv);
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if (ret)
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return ret;
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ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
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0, 0, 0);
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if (ret)
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goto deinit_controller;
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return 0;
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deinit_controller:
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tegra_ahci_controller_deinit(hpriv);
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return ret;
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};
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static struct platform_driver tegra_ahci_driver = {
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.probe = tegra_ahci_probe,
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.remove = ata_platform_remove_one,
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.driver = {
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.name = "tegra-ahci",
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.of_match_table = tegra_ahci_of_match,
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},
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/* LP0 suspend support not implemented */
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};
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module_platform_driver(tegra_ahci_driver);
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MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
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MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
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MODULE_LICENSE("GPL v2");
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