Vipul Pandya 42b6a94990 RDMA/cxgb4: Use DSGLs for fastreg and adapter memory writes for T5. ... It enables direct DMA by HW to memory region PBL arrays and fast register PBL arrays from host memory, vs the T4 way of passing these arrays in the WR itself. The result is lower latency for memory registration, and larger PBL array support for fast register operations. This patch also updates ULP_TX_MEM_WRITE command fields for T5. Ordering bit of ULP_TX_MEM_WRITE is at bit position 22 in T5 and at 23 in T4. Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2013-03-14 11:35:59 -04:00
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cxgb	chelsio: Use netdev_<level> and pr_<level>	2013-01-07 19:40:30 -08:00
cxgb3	cxgb3: Update VLAN extraction stats in the GRO path	2013-02-04 13:22:32 -05:00
cxgb4	RDMA/cxgb4: Use DSGLs for fastreg and adapter memory writes for T5.	2013-03-14 11:35:59 -04:00
cxgb4vf	cxgb4vf: Add support for Chelsio T5 adapter	2013-03-14 11:35:57 -04:00
Kconfig	cxgb3: Restore dependency on INET	2012-11-28 17:40:59 -05:00
Makefile	chelsio: Move the Chelsio drivers	2011-08-10 19:54:52 -07:00