87 lines
1.9 KiB
C
87 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/time.h>
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#include "common.h"
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static const char *clk_cpu(int *idx)
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{
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switch (ralink_soc) {
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case RT2880_SOC:
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*idx = 0;
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return "ralink,rt2880-sysc";
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case RT3883_SOC:
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*idx = 0;
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return "ralink,rt3883-sysc";
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case RT305X_SOC_RT3050:
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*idx = 0;
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return "ralink,rt3050-sysc";
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case RT305X_SOC_RT3052:
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*idx = 0;
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return "ralink,rt3052-sysc";
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case RT305X_SOC_RT3350:
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*idx = 1;
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return "ralink,rt3350-sysc";
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case RT305X_SOC_RT3352:
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*idx = 1;
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return "ralink,rt3352-sysc";
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case RT305X_SOC_RT5350:
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*idx = 1;
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return "ralink,rt5350-sysc";
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case MT762X_SOC_MT7620A:
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*idx = 2;
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return "ralink,mt7620-sysc";
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case MT762X_SOC_MT7620N:
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*idx = 2;
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return "ralink,mt7620-sysc";
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case MT762X_SOC_MT7628AN:
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*idx = 1;
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return "ralink,mt7628-sysc";
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case MT762X_SOC_MT7688:
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*idx = 1;
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return "ralink,mt7688-sysc";
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default:
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*idx = -1;
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return "invalid";
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}
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}
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void __init plat_time_init(void)
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{
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struct of_phandle_args clkspec;
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const char *compatible;
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struct clk *clk;
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int cpu_clk_idx;
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ralink_of_remap();
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compatible = clk_cpu(&cpu_clk_idx);
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if (cpu_clk_idx == -1)
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panic("unable to get CPU clock index");
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of_clk_init(NULL);
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clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
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clkspec.args_count = 1;
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clkspec.args[0] = cpu_clk_idx;
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clk = of_clk_get_from_provider(&clkspec);
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if (IS_ERR(clk))
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panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
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pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
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mips_hpt_frequency = clk_get_rate(clk) / 2;
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clk_put(clk);
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timer_probe();
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}
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