548 lines
14 KiB
C
548 lines
14 KiB
C
#ifndef _ASM_X86_APIC_H
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#define _ASM_X86_APIC_H
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#include <linux/cpumask.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <asm/apicdef.h>
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#include <linux/atomic.h>
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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#include <asm/msr.h>
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#include <asm/hardirq.h>
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/* Macros for apic_extnmi which controls external NMI masking */
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#define APIC_EXTNMI_BSP 0 /* Default */
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#define APIC_EXTNMI_ALL 1
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#define APIC_EXTNMI_NONE 2
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
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extern void generic_apic_probe(void);
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#else
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static inline void generic_apic_probe(void)
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{
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}
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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extern unsigned int apic_verbosity;
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extern int local_apic_timer_c2_ok;
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extern int disable_apic;
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extern unsigned int lapic_timer_frequency;
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extern enum apic_intr_mode_id apic_intr_mode;
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enum apic_intr_mode_id {
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APIC_PIC,
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APIC_VIRTUAL_WIRE,
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APIC_VIRTUAL_WIRE_NO_CONFIG,
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APIC_SYMMETRIC_IO,
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APIC_SYMMETRIC_IO_NO_ROUTING
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};
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#ifdef CONFIG_SMP
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extern void __inquire_remote_apic(int apicid);
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#else /* CONFIG_SMP */
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static inline void __inquire_remote_apic(int apicid)
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{
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}
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#endif /* CONFIG_SMP */
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static inline void default_inquire_remote_apic(int apicid)
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{
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if (apic_verbosity >= APIC_DEBUG)
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__inquire_remote_apic(apicid);
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}
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/*
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* With 82489DX we can't rely on apic feature bit
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* retrieved via cpuid but still have to deal with
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* such an apic chip so we assume that SMP configuration
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* is found from MP table (64bit case uses ACPI mostly
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* which set smp presence flag as well so we are safe
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* to use this helper too).
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*/
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static inline bool apic_from_smp_config(void)
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{
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return smp_found_config && !disable_apic;
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}
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#endif
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extern int setup_profiling_timer(unsigned int);
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static inline void native_apic_mem_write(u32 reg, u32 v)
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{
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volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
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alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
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ASM_OUTPUT2("=r" (v), "=m" (*addr)),
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ASM_OUTPUT2("0" (v), "m" (*addr)));
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}
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static inline u32 native_apic_mem_read(u32 reg)
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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extern void native_apic_wait_icr_idle(void);
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extern u32 native_safe_apic_wait_icr_idle(void);
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extern void native_apic_icr_write(u32 low, u32 id);
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extern u64 native_apic_icr_read(void);
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static inline bool apic_is_x2apic_enabled(void)
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{
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u64 msr;
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if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
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return false;
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return msr & X2APIC_ENABLE;
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}
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extern void enable_IR_x2apic(void);
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extern int get_physical_broadcast(void);
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void apic_intr_mode_init(void);
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extern void init_apic_mappings(void);
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void register_lapic_address(unsigned long address);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern void lapic_update_tsc_freq(void);
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#ifdef CONFIG_X86_64
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static inline int apic_force_enable(unsigned long addr)
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{
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return -1;
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}
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#else
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extern int apic_force_enable(unsigned long addr);
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#endif
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extern void apic_bsp_setup(bool upmode);
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extern void apic_ap_setup(void);
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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extern int apic_is_clustered_box(void);
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#else
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static inline int apic_is_clustered_box(void)
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{
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return 0;
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}
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#endif
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extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
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extern void lapic_assign_system_vectors(void);
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extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
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extern void lapic_online(void);
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extern void lapic_offline(void);
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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static inline void init_apic_mappings(void) { }
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static inline void disable_local_APIC(void) { }
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# define setup_boot_APIC_clock x86_init_noop
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# define setup_secondary_APIC_clock x86_init_noop
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static inline void lapic_update_tsc_freq(void) { }
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static inline void init_bsp_APIC(void) { }
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static inline void apic_intr_mode_init(void) { }
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static inline void lapic_assign_system_vectors(void) { }
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static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_X86_X2APIC
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/*
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* Make previous memory operations globally visible before
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* sending the IPI through x2apic wrmsr. We need a serializing instruction or
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* mfence for this.
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*/
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static inline void x2apic_wrmsr_fence(void)
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{
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asm volatile("mfence" : : : "memory");
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}
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static inline void native_apic_msr_write(u32 reg, u32 v)
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{
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if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
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reg == APIC_LVR)
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return;
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wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
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}
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static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
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{
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__wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
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}
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static inline u32 native_apic_msr_read(u32 reg)
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{
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u64 msr;
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if (reg == APIC_DFR)
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return -1;
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rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
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return (u32)msr;
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}
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static inline void native_x2apic_wait_icr_idle(void)
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{
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/* no need to wait for icr idle in x2apic */
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return;
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}
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static inline u32 native_safe_x2apic_wait_icr_idle(void)
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{
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/* no need to wait for icr idle in x2apic */
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return 0;
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}
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static inline void native_x2apic_icr_write(u32 low, u32 id)
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{
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wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
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}
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static inline u64 native_x2apic_icr_read(void)
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{
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unsigned long val;
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rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
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return val;
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}
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extern int x2apic_mode;
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extern int x2apic_phys;
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extern void __init check_x2apic(void);
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extern void x2apic_setup(void);
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static inline int x2apic_enabled(void)
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{
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return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
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}
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#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
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#else /* !CONFIG_X86_X2APIC */
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static inline void check_x2apic(void) { }
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static inline void x2apic_setup(void) { }
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static inline int x2apic_enabled(void) { return 0; }
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#define x2apic_mode (0)
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#define x2apic_supported() (0)
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#endif /* !CONFIG_X86_X2APIC */
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struct irq_data;
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/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Generic APIC sub-arch data struct.
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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struct apic {
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/* Hotpath functions first */
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void (*eoi_write)(u32 reg, u32 v);
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void (*native_eoi_write)(u32 reg, u32 v);
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void (*write)(u32 reg, u32 v);
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u32 (*read)(u32 reg);
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/* IPI related functions */
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void (*wait_icr_idle)(void);
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u32 (*safe_wait_icr_idle)(void);
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void (*send_IPI)(int cpu, int vector);
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void (*send_IPI_mask)(const struct cpumask *mask, int vector);
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void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
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void (*send_IPI_allbutself)(int vector);
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void (*send_IPI_all)(int vector);
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void (*send_IPI_self)(int vector);
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/* dest_logical is used by the IPI functions */
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u32 dest_logical;
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u32 disable_esr;
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u32 irq_delivery_mode;
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u32 irq_dest_mode;
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u32 (*calc_dest_apicid)(unsigned int cpu);
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/* ICR related functions */
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u64 (*icr_read)(void);
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void (*icr_write)(u32 low, u32 high);
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/* Probe, setup and smpboot functions */
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int (*probe)(void);
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int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
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int (*apic_id_valid)(u32 apicid);
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int (*apic_id_registered)(void);
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bool (*check_apicid_used)(physid_mask_t *map, int apicid);
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void (*init_apic_ldr)(void);
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void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
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void (*setup_apic_routing)(void);
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int (*cpu_present_to_apicid)(int mps_cpu);
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void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
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int (*check_phys_apicid_present)(int phys_apicid);
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int (*phys_pkg_id)(int cpuid_apic, int index_msb);
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u32 (*get_apic_id)(unsigned long x);
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u32 (*set_apic_id)(unsigned int id);
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/* wakeup_secondary_cpu */
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int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
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void (*inquire_remote_apic)(int apicid);
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#ifdef CONFIG_X86_32
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/*
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* Called very early during boot from get_smp_config(). It should
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* return the logical apicid. x86_[bios]_cpu_to_apicid is
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* initialized before this function is called.
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*
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* If logical apicid can't be determined that early, the function
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* may return BAD_APICID. Logical apicid will be configured after
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* init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
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* won't be applied properly during early boot in this case.
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*/
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int (*x86_32_early_logical_apicid)(int cpu);
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#endif
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char *name;
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};
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/*
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* Pointer to the local APIC driver in use on this system (there's
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* always just one such driver in use - the kernel decides via an
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* early probing process which one it picks - and then sticks to it):
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*/
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extern struct apic *apic;
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/*
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* APIC drivers are probed based on how they are listed in the .apicdrivers
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* section. So the order is important and enforced by the ordering
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* of different apic driver files in the Makefile.
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*
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* For the files having two apic drivers, we use apic_drivers()
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* to enforce the order with in them.
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*/
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#define apic_driver(sym) \
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static const struct apic *__apicdrivers_##sym __used \
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__aligned(sizeof(struct apic *)) \
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__section(.apicdrivers) = { &sym }
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#define apic_drivers(sym1, sym2) \
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static struct apic *__apicdrivers_##sym1##sym2[2] __used \
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__aligned(sizeof(struct apic *)) \
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__section(.apicdrivers) = { &sym1, &sym2 }
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extern struct apic *__apicdrivers[], *__apicdrivers_end[];
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/*
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* APIC functionality to boot other CPUs - only used on SMP:
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*/
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#ifdef CONFIG_SMP
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extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
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extern int lapic_can_unplug_cpu(void);
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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static inline u32 apic_read(u32 reg)
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{
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return apic->read(reg);
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}
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static inline void apic_write(u32 reg, u32 val)
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{
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apic->write(reg, val);
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}
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static inline void apic_eoi(void)
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{
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apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
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}
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static inline u64 apic_icr_read(void)
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{
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return apic->icr_read();
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}
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static inline void apic_icr_write(u32 low, u32 high)
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{
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apic->icr_write(low, high);
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}
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static inline void apic_wait_icr_idle(void)
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{
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apic->wait_icr_idle();
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}
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static inline u32 safe_apic_wait_icr_idle(void)
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{
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return apic->safe_wait_icr_idle();
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}
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extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
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#else /* CONFIG_X86_LOCAL_APIC */
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static inline u32 apic_read(u32 reg) { return 0; }
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static inline void apic_write(u32 reg, u32 val) { }
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static inline void apic_eoi(void) { }
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static inline u64 apic_icr_read(void) { return 0; }
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static inline void apic_icr_write(u32 low, u32 high) { }
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static inline void apic_wait_icr_idle(void) { }
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static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
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static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
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#endif /* CONFIG_X86_LOCAL_APIC */
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extern void apic_ack_irq(struct irq_data *data);
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction
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* ... yummie.
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*/
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apic_eoi();
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}
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static inline unsigned default_get_apic_id(unsigned long x)
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{
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unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
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if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
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return (x >> 24) & 0xFF;
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else
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return (x >> 24) & 0x0F;
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}
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/*
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* Warm reset vector position:
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*/
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#define TRAMPOLINE_PHYS_LOW 0x467
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#define TRAMPOLINE_PHYS_HIGH 0x469
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#ifdef CONFIG_X86_64
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extern void apic_send_IPI_self(int vector);
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DECLARE_PER_CPU(int, x2apic_extra_bits);
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#endif
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extern void generic_bigsmp_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/smp.h>
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
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extern struct apic apic_noop;
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static inline unsigned int read_apic_id(void)
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{
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unsigned int reg = apic_read(APIC_ID);
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return apic->get_apic_id(reg);
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}
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extern int default_apic_id_valid(u32 apicid);
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extern int default_acpi_madt_oem_check(char *, char *);
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extern void default_setup_apic_routing(void);
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extern u32 apic_default_calc_apicid(unsigned int cpu);
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extern u32 apic_flat_calc_apicid(unsigned int cpu);
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extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
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extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
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extern int default_cpu_present_to_apicid(int mps_cpu);
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extern int default_check_phys_apicid_present(int phys_apicid);
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#endif /* CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_SMP
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bool apic_id_is_primary_thread(unsigned int id);
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#else
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static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
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#endif
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extern void irq_enter(void);
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extern void irq_exit(void);
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static inline void entering_irq(void)
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{
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irq_enter();
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kvm_set_cpu_l1tf_flush_l1d();
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}
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static inline void entering_ack_irq(void)
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{
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entering_irq();
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ack_APIC_irq();
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}
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static inline void ipi_entering_ack_irq(void)
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{
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irq_enter();
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ack_APIC_irq();
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kvm_set_cpu_l1tf_flush_l1d();
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}
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static inline void exiting_irq(void)
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{
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irq_exit();
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}
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static inline void exiting_ack_irq(void)
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{
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ack_APIC_irq();
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irq_exit();
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}
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extern void ioapic_zap_locks(void);
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#endif /* _ASM_X86_APIC_H */
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