434 lines
14 KiB
C
434 lines
14 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_MES_H__
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#define __AMDGPU_MES_H__
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#include "amdgpu_irq.h"
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#include "kgd_kfd_interface.h"
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#include "amdgpu_gfx.h"
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#include <linux/sched/mm.h>
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#define AMDGPU_MES_MAX_COMPUTE_PIPES 8
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#define AMDGPU_MES_MAX_GFX_PIPES 2
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#define AMDGPU_MES_MAX_SDMA_PIPES 2
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#define AMDGPU_MES_API_VERSION_SHIFT 12
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#define AMDGPU_MES_FEAT_VERSION_SHIFT 24
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#define AMDGPU_MES_VERSION_MASK 0x00000fff
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#define AMDGPU_MES_API_VERSION_MASK 0x00fff000
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#define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000
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enum amdgpu_mes_priority_level {
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AMDGPU_MES_PRIORITY_LEVEL_LOW = 0,
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AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1,
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AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2,
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AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3,
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AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4,
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AMDGPU_MES_PRIORITY_NUM_LEVELS
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};
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#define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
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#define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
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struct amdgpu_mes_funcs;
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enum admgpu_mes_pipe {
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AMDGPU_MES_SCHED_PIPE = 0,
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AMDGPU_MES_KIQ_PIPE,
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AMDGPU_MAX_MES_PIPES = 2,
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};
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struct amdgpu_mes {
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struct amdgpu_device *adev;
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struct mutex mutex_hidden;
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struct idr pasid_idr;
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struct idr gang_id_idr;
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struct idr queue_id_idr;
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struct ida doorbell_ida;
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spinlock_t queue_id_lock;
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uint32_t sched_version;
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uint32_t kiq_version;
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uint32_t total_max_queue;
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uint32_t doorbell_id_offset;
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uint32_t max_doorbell_slices;
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uint64_t default_process_quantum;
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uint64_t default_gang_quantum;
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struct amdgpu_ring ring;
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spinlock_t ring_lock;
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const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
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/* mes ucode */
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struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
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uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
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uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
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uint32_t ucode_fw_version[AMDGPU_MAX_MES_PIPES];
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uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
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/* mes ucode data */
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struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
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uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
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uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
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uint32_t data_fw_version[AMDGPU_MAX_MES_PIPES];
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uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
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/* eop gpu obj */
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struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
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uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
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void *mqd_backup[AMDGPU_MAX_MES_PIPES];
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struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
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uint32_t vmid_mask_gfxhub;
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uint32_t vmid_mask_mmhub;
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uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
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uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
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uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
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uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
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uint32_t sch_ctx_offs;
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uint64_t sch_ctx_gpu_addr;
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uint64_t *sch_ctx_ptr;
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uint32_t query_status_fence_offs;
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uint64_t query_status_fence_gpu_addr;
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uint64_t *query_status_fence_ptr;
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uint32_t read_val_offs;
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uint64_t read_val_gpu_addr;
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uint32_t *read_val_ptr;
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uint32_t saved_flags;
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/* initialize kiq pipe */
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int (*kiq_hw_init)(struct amdgpu_device *adev);
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int (*kiq_hw_fini)(struct amdgpu_device *adev);
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/* ip specific functions */
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const struct amdgpu_mes_funcs *funcs;
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};
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struct amdgpu_mes_process {
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int pasid;
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struct amdgpu_vm *vm;
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uint64_t pd_gpu_addr;
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struct amdgpu_bo *proc_ctx_bo;
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uint64_t proc_ctx_gpu_addr;
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void *proc_ctx_cpu_ptr;
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uint64_t process_quantum;
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struct list_head gang_list;
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uint32_t doorbell_index;
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unsigned long *doorbell_bitmap;
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struct mutex doorbell_lock;
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};
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struct amdgpu_mes_gang {
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int gang_id;
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int priority;
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int inprocess_gang_priority;
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int global_priority_level;
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struct list_head list;
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struct amdgpu_mes_process *process;
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struct amdgpu_bo *gang_ctx_bo;
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uint64_t gang_ctx_gpu_addr;
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void *gang_ctx_cpu_ptr;
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uint64_t gang_quantum;
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struct list_head queue_list;
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};
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struct amdgpu_mes_queue {
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struct list_head list;
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struct amdgpu_mes_gang *gang;
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int queue_id;
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uint64_t doorbell_off;
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struct amdgpu_bo *mqd_obj;
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void *mqd_cpu_ptr;
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uint64_t mqd_gpu_addr;
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uint64_t wptr_gpu_addr;
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int queue_type;
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int paging;
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struct amdgpu_ring *ring;
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};
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struct amdgpu_mes_queue_properties {
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int queue_type;
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uint64_t hqd_base_gpu_addr;
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uint64_t rptr_gpu_addr;
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uint64_t wptr_gpu_addr;
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uint64_t wptr_mc_addr;
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uint32_t queue_size;
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uint64_t eop_gpu_addr;
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uint32_t hqd_pipe_priority;
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uint32_t hqd_queue_priority;
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bool paging;
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struct amdgpu_ring *ring;
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/* out */
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uint64_t doorbell_off;
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};
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struct amdgpu_mes_gang_properties {
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uint32_t priority;
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uint32_t gang_quantum;
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uint32_t inprocess_gang_priority;
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uint32_t priority_level;
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int global_priority_level;
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};
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struct mes_add_queue_input {
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uint32_t process_id;
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uint64_t page_table_base_addr;
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uint64_t process_va_start;
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uint64_t process_va_end;
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uint64_t process_quantum;
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uint64_t process_context_addr;
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uint64_t gang_quantum;
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uint64_t gang_context_addr;
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uint32_t inprocess_gang_priority;
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uint32_t gang_global_priority_level;
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uint32_t doorbell_offset;
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uint64_t mqd_addr;
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uint64_t wptr_addr;
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uint64_t wptr_mc_addr;
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uint32_t queue_type;
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uint32_t paging;
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uint32_t gws_base;
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uint32_t gws_size;
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uint64_t tba_addr;
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uint64_t tma_addr;
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uint32_t is_kfd_process;
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uint32_t is_aql_queue;
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uint32_t queue_size;
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};
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struct mes_remove_queue_input {
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uint32_t doorbell_offset;
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uint64_t gang_context_addr;
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};
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struct mes_unmap_legacy_queue_input {
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enum amdgpu_unmap_queues_action action;
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uint32_t queue_type;
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uint32_t doorbell_offset;
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uint32_t pipe_id;
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uint32_t queue_id;
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uint64_t trail_fence_addr;
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uint64_t trail_fence_data;
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};
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struct mes_suspend_gang_input {
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bool suspend_all_gangs;
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uint64_t gang_context_addr;
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uint64_t suspend_fence_addr;
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uint32_t suspend_fence_value;
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};
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struct mes_resume_gang_input {
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bool resume_all_gangs;
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uint64_t gang_context_addr;
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};
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enum mes_misc_opcode {
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MES_MISC_OP_WRITE_REG,
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MES_MISC_OP_READ_REG,
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MES_MISC_OP_WRM_REG_WAIT,
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MES_MISC_OP_WRM_REG_WR_WAIT,
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};
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struct mes_misc_op_input {
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enum mes_misc_opcode op;
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union {
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struct {
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uint32_t reg_offset;
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uint64_t buffer_addr;
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} read_reg;
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struct {
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uint32_t reg_offset;
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uint32_t reg_value;
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} write_reg;
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struct {
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uint32_t ref;
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uint32_t mask;
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uint32_t reg0;
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uint32_t reg1;
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} wrm_reg;
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};
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};
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struct amdgpu_mes_funcs {
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int (*add_hw_queue)(struct amdgpu_mes *mes,
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struct mes_add_queue_input *input);
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int (*remove_hw_queue)(struct amdgpu_mes *mes,
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struct mes_remove_queue_input *input);
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int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
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struct mes_unmap_legacy_queue_input *input);
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int (*suspend_gang)(struct amdgpu_mes *mes,
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struct mes_suspend_gang_input *input);
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int (*resume_gang)(struct amdgpu_mes *mes,
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struct mes_resume_gang_input *input);
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int (*misc_op)(struct amdgpu_mes *mes,
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struct mes_misc_op_input *input);
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};
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#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
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#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
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int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
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int amdgpu_mes_init(struct amdgpu_device *adev);
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void amdgpu_mes_fini(struct amdgpu_device *adev);
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int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,
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struct amdgpu_vm *vm);
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void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);
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int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,
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struct amdgpu_mes_gang_properties *gprops,
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int *gang_id);
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int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);
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int amdgpu_mes_suspend(struct amdgpu_device *adev);
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int amdgpu_mes_resume(struct amdgpu_device *adev);
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int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
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struct amdgpu_mes_queue_properties *qprops,
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int *queue_id);
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int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
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int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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enum amdgpu_unmap_queues_action action,
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u64 gpu_addr, u64 seq);
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uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
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int amdgpu_mes_wreg(struct amdgpu_device *adev,
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uint32_t reg, uint32_t val);
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int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
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uint32_t val, uint32_t mask);
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int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask);
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int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
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int queue_type, int idx,
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struct amdgpu_mes_ctx_data *ctx_data,
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struct amdgpu_ring **out);
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void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
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struct amdgpu_ring *ring);
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uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
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enum amdgpu_mes_priority_level prio);
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int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
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struct amdgpu_mes_ctx_data *ctx_data);
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void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);
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int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_mes_ctx_data *ctx_data);
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int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
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struct amdgpu_mes_ctx_data *ctx_data);
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int amdgpu_mes_self_test(struct amdgpu_device *adev);
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int amdgpu_mes_alloc_process_doorbells(struct amdgpu_device *adev,
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unsigned int *doorbell_index);
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void amdgpu_mes_free_process_doorbells(struct amdgpu_device *adev,
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unsigned int doorbell_index);
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unsigned int amdgpu_mes_get_doorbell_dw_offset_in_bar(
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struct amdgpu_device *adev,
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uint32_t doorbell_index,
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unsigned int doorbell_id);
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int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
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/*
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* MES lock can be taken in MMU notifiers.
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*
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* A bit more detail about why to set no-FS reclaim with MES lock:
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*
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* The purpose of the MMU notifier is to stop GPU access to memory so
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* that the Linux VM subsystem can move pages around safely. This is
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* done by preempting user mode queues for the affected process. When
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* MES is used, MES lock needs to be taken to preempt the queues.
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*
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* The MMU notifier callback entry point in the driver is
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* amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
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* there is:
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* amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
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* kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
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*
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* The last part of the chain is a function pointer where we take the
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* MES lock.
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*
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* The problem with taking locks in the MMU notifier is, that MMU
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* notifiers can be called in reclaim-FS context. That's where the
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* kernel frees up pages to make room for new page allocations under
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* memory pressure. While we are running in reclaim-FS context, we must
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* not trigger another memory reclaim operation because that would
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* recursively reenter the reclaim code and cause a deadlock. The
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* memalloc_nofs_save/restore calls guarantee that.
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*
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* In addition we also need to avoid lock dependencies on other locks taken
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* under the MES lock, for example reservation locks. Here is a possible
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* scenario of a deadlock:
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* Thread A: takes and holds reservation lock | triggers reclaim-FS |
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* MMU notifier | blocks trying to take MES lock
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* Thread B: takes and holds MES lock | blocks trying to take reservation lock
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*
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* In this scenario Thread B gets involved in a deadlock even without
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* triggering a reclaim-FS operation itself.
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* To fix this and break the lock dependency chain you'd need to either:
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* 1. protect reservation locks with memalloc_nofs_save/restore, or
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* 2. avoid taking reservation locks under the MES lock.
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*
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* Reservation locks are taken all over the kernel in different subsystems, we
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* have no control over them and their lock dependencies.So the only workable
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* solution is to avoid taking other locks under the MES lock.
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* As a result, make sure no reclaim-FS happens while holding this lock anywhere
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* to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
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*/
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static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
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{
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mutex_lock(&mes->mutex_hidden);
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mes->saved_flags = memalloc_noreclaim_save();
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}
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static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
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{
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memalloc_noreclaim_restore(mes->saved_flags);
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mutex_unlock(&mes->mutex_hidden);
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}
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#endif /* __AMDGPU_MES_H__ */
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