434 lines
14 KiB
C
434 lines
14 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
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#ifndef AMDGPU_AMDKFD_H_INCLUDED
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#define AMDGPU_AMDKFD_H_INCLUDED
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/kthread.h>
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#include <linux/workqueue.h>
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#include <kgd_kfd_interface.h>
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#include <drm/ttm/ttm_execbuf_util.h>
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#include "amdgpu_sync.h"
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#include "amdgpu_vm.h"
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extern uint64_t amdgpu_amdkfd_total_mem_size;
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enum TLB_FLUSH_TYPE {
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TLB_FLUSH_LEGACY = 0,
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TLB_FLUSH_LIGHTWEIGHT,
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TLB_FLUSH_HEAVYWEIGHT
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};
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struct amdgpu_device;
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enum kfd_mem_attachment_type {
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KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
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KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
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KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
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KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */
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};
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struct kfd_mem_attachment {
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struct list_head list;
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enum kfd_mem_attachment_type type;
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bool is_mapped;
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struct amdgpu_bo_va *bo_va;
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struct amdgpu_device *adev;
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uint64_t va;
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uint64_t pte_flags;
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};
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struct kgd_mem {
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struct mutex lock;
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struct amdgpu_bo *bo;
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struct dma_buf *dmabuf;
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struct list_head attachments;
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/* protected by amdkfd_process_info.lock */
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struct ttm_validate_buffer validate_list;
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struct ttm_validate_buffer resv_list;
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uint32_t domain;
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unsigned int mapped_to_gpu_memory;
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uint64_t va;
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uint32_t alloc_flags;
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atomic_t invalid;
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struct amdkfd_process_info *process_info;
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struct amdgpu_sync sync;
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bool aql_queue;
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bool is_imported;
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};
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/* KFD Memory Eviction */
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struct amdgpu_amdkfd_fence {
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struct dma_fence base;
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struct mm_struct *mm;
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spinlock_t lock;
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char timeline_name[TASK_COMM_LEN];
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struct svm_range_bo *svm_bo;
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};
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struct amdgpu_kfd_dev {
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struct kfd_dev *dev;
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uint64_t vram_used;
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uint64_t vram_used_aligned;
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bool init_complete;
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struct work_struct reset_work;
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};
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enum kgd_engine_type {
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KGD_ENGINE_PFP = 1,
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KGD_ENGINE_ME,
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KGD_ENGINE_CE,
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KGD_ENGINE_MEC1,
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KGD_ENGINE_MEC2,
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KGD_ENGINE_RLC,
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KGD_ENGINE_SDMA1,
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KGD_ENGINE_SDMA2,
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KGD_ENGINE_MAX
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};
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struct amdkfd_process_info {
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/* List head of all VMs that belong to a KFD process */
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struct list_head vm_list_head;
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/* List head for all KFD BOs that belong to a KFD process. */
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struct list_head kfd_bo_list;
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/* List of userptr BOs that are valid or invalid */
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struct list_head userptr_valid_list;
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struct list_head userptr_inval_list;
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/* Lock to protect kfd_bo_list */
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struct mutex lock;
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/* Number of VMs */
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unsigned int n_vms;
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/* Eviction Fence */
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struct amdgpu_amdkfd_fence *eviction_fence;
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/* MMU-notifier related fields */
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atomic_t evicted_bos;
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struct delayed_work restore_userptr_work;
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struct pid *pid;
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bool block_mmu_notifications;
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};
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int amdgpu_amdkfd_init(void);
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void amdgpu_amdkfd_fini(void);
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void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
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int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev);
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int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
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void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
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const void *ih_ring_entry);
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void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
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void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
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void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
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int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
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enum kgd_engine_type engine,
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uint32_t vmid, uint64_t gpu_addr,
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uint32_t *ib_cmd, uint32_t ib_len);
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void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
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bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
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int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
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uint16_t vmid);
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int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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uint16_t pasid, enum TLB_FLUSH_TYPE flush_type);
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bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
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int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
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int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
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void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);
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int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
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int queue_bit);
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struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
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struct mm_struct *mm,
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struct svm_range_bo *svm_bo);
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#if defined(CONFIG_DEBUG_FS)
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int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
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#endif
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#if IS_ENABLED(CONFIG_HSA_AMD)
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bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
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struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
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int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
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int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
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#else
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static inline
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bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
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{
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return false;
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}
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static inline
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struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
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{
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return NULL;
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}
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static inline
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int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
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{
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return 0;
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}
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static inline
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int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
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{
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return 0;
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}
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#endif
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/* Shared API */
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int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
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void **mem_obj, uint64_t *gpu_addr,
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void **cpu_ptr, bool mqd_gfx9);
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void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj);
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int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
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void **mem_obj);
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void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
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int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
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int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
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uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
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enum kgd_engine_type type);
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void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
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struct kfd_local_mem_info *mem_info);
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uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
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uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
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void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev,
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struct kfd_cu_info *cu_info);
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int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
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struct amdgpu_device **dmabuf_adev,
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uint64_t *bo_size, void *metadata_buffer,
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size_t buffer_size, uint32_t *metadata_size,
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uint32_t *flags);
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uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
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struct amdgpu_device *src);
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int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
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struct amdgpu_device *src,
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bool is_min);
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int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
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/* Read user wptr from a specified user address space with page fault
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* disabled. The memory must be pinned and mapped to the hardware when
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* this is called in hqd_load functions, so it should never fault in
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* the first place. This resolves a circular lock dependency involving
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* four locks, including the DQM lock and mmap_lock.
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*/
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#define read_user_wptr(mmptr, wptr, dst) \
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({ \
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bool valid = false; \
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if ((mmptr) && (wptr)) { \
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pagefault_disable(); \
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if ((mmptr) == current->mm) { \
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valid = !get_user((dst), (wptr)); \
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} else if (current->flags & PF_KTHREAD) { \
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kthread_use_mm(mmptr); \
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valid = !get_user((dst), (wptr)); \
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kthread_unuse_mm(mmptr); \
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} \
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pagefault_enable(); \
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} \
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valid; \
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})
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/* GPUVM API */
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#define drm_priv_to_vm(drm_priv) \
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(&((struct amdgpu_fpriv *) \
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((struct drm_file *)(drm_priv))->driver_priv)->vm)
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int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
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struct file *filp, u32 pasid,
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void **process_info,
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struct dma_fence **ef);
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void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
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void *drm_priv);
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uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
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size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev);
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int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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struct amdgpu_device *adev, uint64_t va, uint64_t size,
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void *drm_priv, struct kgd_mem **mem,
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uint64_t *offset, uint32_t flags, bool criu_resume);
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int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
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struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
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uint64_t *size);
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int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
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struct kgd_mem *mem, void *drm_priv);
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int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
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struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
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int amdgpu_amdkfd_gpuvm_sync_memory(
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struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
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int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
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void **kptr, uint64_t *size);
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void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
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int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo);
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int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
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struct dma_fence **ef);
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int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
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struct kfd_vm_fault_info *info);
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int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
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struct dma_buf *dmabuf,
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uint64_t va, void *drm_priv,
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struct kgd_mem **mem, uint64_t *size,
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uint64_t *mmap_offset);
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int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
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struct tile_config *config);
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void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
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bool reset);
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bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);
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void amdgpu_amdkfd_block_mmu_notifications(void *p);
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int amdgpu_amdkfd_criu_resume(void *p);
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bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
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int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
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uint64_t size, u32 alloc_flag);
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void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
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uint64_t size, u32 alloc_flag);
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#if IS_ENABLED(CONFIG_HSA_AMD)
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void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
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void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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/**
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* @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
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*
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* Allows KFD to release its resources associated with the GEM object.
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*/
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void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
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void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
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#else
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static inline
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void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
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{
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}
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static inline
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void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
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struct amdgpu_vm *vm)
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{
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}
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static inline
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void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
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{
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}
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#endif
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/* KGD2KFD callbacks */
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int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
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int kgd2kfd_resume_mm(struct mm_struct *mm);
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int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
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struct dma_fence *fence);
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#if IS_ENABLED(CONFIG_HSA_AMD)
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int kgd2kfd_init(void);
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void kgd2kfd_exit(void);
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struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
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bool kgd2kfd_device_init(struct kfd_dev *kfd,
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struct drm_device *ddev,
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const struct kgd2kfd_shared_resources *gpu_resources);
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void kgd2kfd_device_exit(struct kfd_dev *kfd);
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void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
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int kgd2kfd_resume_iommu(struct kfd_dev *kfd);
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int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
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int kgd2kfd_pre_reset(struct kfd_dev *kfd);
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int kgd2kfd_post_reset(struct kfd_dev *kfd);
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void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
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void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
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void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
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#else
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static inline int kgd2kfd_init(void)
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{
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return -ENOENT;
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}
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static inline void kgd2kfd_exit(void)
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{
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}
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static inline
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struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
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{
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return NULL;
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}
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static inline
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bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev,
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const struct kgd2kfd_shared_resources *gpu_resources)
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{
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return false;
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}
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static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
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{
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}
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static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
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{
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}
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static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd)
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{
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return 0;
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}
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static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
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{
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return 0;
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}
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static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
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{
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return 0;
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}
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static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
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{
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return 0;
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}
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static inline
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void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
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{
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}
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static inline
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void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
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{
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}
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static inline
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void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
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{
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}
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#endif
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#endif /* AMDGPU_AMDKFD_H_INCLUDED */
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