509 lines
12 KiB
C
509 lines
12 KiB
C
/*
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* linux/arch/arm/vfp/vfpmodule.c
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <asm/thread_notify.h>
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#include <asm/vfp.h>
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#include "vfpinstr.h"
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#include "vfp.h"
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/*
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* Our undef handlers (in entry.S)
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*/
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void vfp_testing_entry(void);
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void vfp_support_entry(void);
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void vfp_null_entry(void);
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void (*vfp_vector)(void) = vfp_null_entry;
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union vfp_state *last_VFP_context[NR_CPUS];
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/*
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* Dual-use variable.
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* Used in startup: set to non-zero if VFP checks fail
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* After startup, holds VFP architecture
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*/
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unsigned int VFP_arch;
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static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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{
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struct thread_info *thread = v;
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union vfp_state *vfp;
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__u32 cpu = thread->cpu;
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if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
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u32 fpexc = fmrx(FPEXC);
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#ifdef CONFIG_SMP
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/*
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* On SMP, if VFP is enabled, save the old state in
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* case the thread migrates to a different CPU. The
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* restoring is done lazily.
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*/
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if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) {
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vfp_save_state(last_VFP_context[cpu], fpexc);
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last_VFP_context[cpu]->hard.cpu = cpu;
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}
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/*
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* Thread migration, just force the reloading of the
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* state on the new CPU in case the VFP registers
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* contain stale data.
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*/
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if (thread->vfpstate.hard.cpu != cpu)
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last_VFP_context[cpu] = NULL;
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#endif
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/*
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* Always disable VFP so we can lazily save/restore the
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* old state.
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*/
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fmxr(FPEXC, fpexc & ~FPEXC_EN);
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return NOTIFY_DONE;
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}
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vfp = &thread->vfpstate;
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if (cmd == THREAD_NOTIFY_FLUSH) {
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/*
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* Per-thread VFP initialisation.
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*/
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memset(vfp, 0, sizeof(union vfp_state));
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vfp->hard.fpexc = FPEXC_EN;
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vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
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/*
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* Disable VFP to ensure we initialise it first.
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*/
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fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
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}
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/* flush and release case: Per-thread VFP cleanup. */
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if (last_VFP_context[cpu] == vfp)
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last_VFP_context[cpu] = NULL;
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return NOTIFY_DONE;
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}
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static struct notifier_block vfp_notifier_block = {
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.notifier_call = vfp_notifier,
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};
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/*
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* Raise a SIGFPE for the current process.
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* sicode describes the signal being raised.
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*/
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void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
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{
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siginfo_t info;
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memset(&info, 0, sizeof(info));
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info.si_signo = SIGFPE;
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info.si_code = sicode;
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info.si_addr = (void __user *)(instruction_pointer(regs) - 4);
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/*
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* This is the same as NWFPE, because it's not clear what
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* this is used for
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*/
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current->thread.error_code = 0;
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current->thread.trap_no = 6;
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send_sig_info(SIGFPE, &info, current);
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}
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static void vfp_panic(char *reason, u32 inst)
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{
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int i;
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printk(KERN_ERR "VFP: Error: %s\n", reason);
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printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
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fmrx(FPEXC), fmrx(FPSCR), inst);
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for (i = 0; i < 32; i += 2)
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printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
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i, vfp_get_float(i), i+1, vfp_get_float(i+1));
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}
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/*
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* Process bitmask of exception conditions.
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*/
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static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs)
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{
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int si_code = 0;
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pr_debug("VFP: raising exceptions %08x\n", exceptions);
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if (exceptions == VFP_EXCEPTION_ERROR) {
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vfp_panic("unhandled bounce", inst);
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vfp_raise_sigfpe(0, regs);
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return;
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}
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/*
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* Update the FPSCR with the additional exception flags.
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* Comparison instructions always return at least one of
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* these flags set.
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*/
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fpscr |= exceptions;
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fmxr(FPSCR, fpscr);
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#define RAISE(stat,en,sig) \
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if (exceptions & stat && fpscr & en) \
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si_code = sig;
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/*
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* These are arranged in priority order, least to highest.
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*/
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RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV);
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RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES);
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RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND);
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RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF);
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RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV);
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if (si_code)
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vfp_raise_sigfpe(si_code, regs);
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}
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/*
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* Emulate a VFP instruction.
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*/
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static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
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{
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u32 exceptions = VFP_EXCEPTION_ERROR;
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pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
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if (INST_CPRTDO(inst)) {
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if (!INST_CPRT(inst)) {
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/*
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* CPDO
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*/
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if (vfp_single(inst)) {
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exceptions = vfp_single_cpdo(inst, fpscr);
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} else {
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exceptions = vfp_double_cpdo(inst, fpscr);
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}
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} else {
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/*
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* A CPRT instruction can not appear in FPINST2, nor
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* can it cause an exception. Therefore, we do not
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* have to emulate it.
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*/
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}
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} else {
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/*
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* A CPDT instruction can not appear in FPINST2, nor can
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* it cause an exception. Therefore, we do not have to
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* emulate it.
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*/
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}
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return exceptions & ~VFP_NAN_FLAG;
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}
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/*
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* Package up a bounce condition.
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*/
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void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
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{
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u32 fpscr, orig_fpscr, fpsid, exceptions;
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pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
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/*
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* At this point, FPEXC can have the following configuration:
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*
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* EX DEX IXE
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* 0 1 x - synchronous exception
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* 1 x 0 - asynchronous exception
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* 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later
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* 0 0 1 - synchronous on VFP9 (non-standard subarch 1
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* implementation), undefined otherwise
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*
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* Clear various bits and enable access to the VFP so we can
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* handle the bounce.
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*/
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fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK));
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fpsid = fmrx(FPSID);
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orig_fpscr = fpscr = fmrx(FPSCR);
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/*
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* Check for the special VFP subarch 1 and FPSCR.IXE bit case
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*/
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if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT)
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&& (fpscr & FPSCR_IXE)) {
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/*
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* Synchronous exception, emulate the trigger instruction
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*/
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goto emulate;
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}
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if (fpexc & FPEXC_EX) {
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#ifndef CONFIG_CPU_FEROCEON
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/*
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* Asynchronous exception. The instruction is read from FPINST
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* and the interrupted instruction has to be restarted.
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*/
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trigger = fmrx(FPINST);
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regs->ARM_pc -= 4;
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#endif
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} else if (!(fpexc & FPEXC_DEX)) {
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/*
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* Illegal combination of bits. It can be caused by an
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* unallocated VFP instruction but with FPSCR.IXE set and not
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* on VFP subarch 1.
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*/
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vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs);
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goto exit;
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}
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/*
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* Modify fpscr to indicate the number of iterations remaining.
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* If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates
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* whether FPEXC.VECITR or FPSCR.LEN is used.
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*/
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if (fpexc & (FPEXC_EX | FPEXC_VV)) {
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u32 len;
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len = fpexc + (1 << FPEXC_LENGTH_BIT);
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fpscr &= ~FPSCR_LENGTH_MASK;
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fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT);
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}
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/*
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* Handle the first FP instruction. We used to take note of the
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* FPEXC bounce reason, but this appears to be unreliable.
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* Emulate the bounced instruction instead.
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*/
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exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
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if (exceptions)
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vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
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/*
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* If there isn't a second FP instruction, exit now. Note that
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* the FPEXC.FP2V bit is valid only if FPEXC.EX is 1.
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*/
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if (fpexc ^ (FPEXC_EX | FPEXC_FP2V))
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goto exit;
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/*
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* The barrier() here prevents fpinst2 being read
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* before the condition above.
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*/
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barrier();
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trigger = fmrx(FPINST2);
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emulate:
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exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs);
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if (exceptions)
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vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
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exit:
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preempt_enable();
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}
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static void vfp_enable(void *unused)
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{
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u32 access = get_copro_access();
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/*
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* Enable full access to VFP (cp10 and cp11)
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*/
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set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
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}
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#ifdef CONFIG_PM
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#include <linux/sysdev.h>
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static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct thread_info *ti = current_thread_info();
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u32 fpexc = fmrx(FPEXC);
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/* if vfp is on, then save state for resumption */
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if (fpexc & FPEXC_EN) {
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printk(KERN_DEBUG "%s: saving vfp state\n", __func__);
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vfp_save_state(&ti->vfpstate, fpexc);
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/* disable, just in case */
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fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
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}
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/* clear any information we had about last context state */
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memset(last_VFP_context, 0, sizeof(last_VFP_context));
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return 0;
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}
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static int vfp_pm_resume(struct sys_device *dev)
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{
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/* ensure we have access to the vfp */
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vfp_enable(NULL);
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/* and disable it to ensure the next usage restores the state */
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fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
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return 0;
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}
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static struct sysdev_class vfp_pm_sysclass = {
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.name = "vfp",
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.suspend = vfp_pm_suspend,
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.resume = vfp_pm_resume,
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};
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static struct sys_device vfp_pm_sysdev = {
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.cls = &vfp_pm_sysclass,
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};
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static void vfp_pm_init(void)
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{
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sysdev_class_register(&vfp_pm_sysclass);
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sysdev_register(&vfp_pm_sysdev);
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}
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#else
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static inline void vfp_pm_init(void) { }
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#endif /* CONFIG_PM */
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/*
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* Synchronise the hardware VFP state of a thread other than current with the
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* saved one. This function is used by the ptrace mechanism.
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*/
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#ifdef CONFIG_SMP
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void vfp_sync_state(struct thread_info *thread)
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{
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/*
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* On SMP systems, the VFP state is automatically saved at every
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* context switch. We mark the thread VFP state as belonging to a
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* non-existent CPU so that the saved one will be reloaded when
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* needed.
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*/
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thread->vfpstate.hard.cpu = NR_CPUS;
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}
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#else
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void vfp_sync_state(struct thread_info *thread)
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{
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unsigned int cpu = get_cpu();
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u32 fpexc = fmrx(FPEXC);
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/*
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* If VFP is enabled, the previous state was already saved and
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* last_VFP_context updated.
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*/
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if (fpexc & FPEXC_EN)
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goto out;
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if (!last_VFP_context[cpu])
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goto out;
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/*
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* Save the last VFP state on this CPU.
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*/
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fmxr(FPEXC, fpexc | FPEXC_EN);
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vfp_save_state(last_VFP_context[cpu], fpexc);
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fmxr(FPEXC, fpexc);
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/*
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* Set the context to NULL to force a reload the next time the thread
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* uses the VFP.
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*/
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last_VFP_context[cpu] = NULL;
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out:
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put_cpu();
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}
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#endif
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#include <linux/smp.h>
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/*
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* VFP support code initialisation.
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*/
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static int __init vfp_init(void)
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{
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unsigned int vfpsid;
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unsigned int cpu_arch = cpu_architecture();
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if (cpu_arch >= CPU_ARCH_ARMv6)
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vfp_enable(NULL);
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/*
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* First check that there is a VFP that we can use.
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* The handler is already setup to just log calls, so
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* we just need to read the VFPSID register.
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*/
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vfp_vector = vfp_testing_entry;
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barrier();
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vfpsid = fmrx(FPSID);
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barrier();
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vfp_vector = vfp_null_entry;
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printk(KERN_INFO "VFP support v0.3: ");
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if (VFP_arch)
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printk("not present\n");
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else if (vfpsid & FPSID_NODOUBLE) {
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printk("no double precision support\n");
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} else {
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smp_call_function(vfp_enable, NULL, 1);
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VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */
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printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
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(vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
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(vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
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(vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
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(vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
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(vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
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vfp_vector = vfp_support_entry;
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thread_register_notifier(&vfp_notifier_block);
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vfp_pm_init();
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/*
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* We detected VFP, and the support code is
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* in place; report VFP support to userspace.
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*/
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elf_hwcap |= HWCAP_VFP;
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#ifdef CONFIG_VFPv3
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if (VFP_arch >= 3) {
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elf_hwcap |= HWCAP_VFPv3;
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/*
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* Check for VFPv3 D16. CPUs in this configuration
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* only have 16 x 64bit registers.
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*/
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if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1)
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elf_hwcap |= HWCAP_VFPv3D16;
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}
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#endif
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#ifdef CONFIG_NEON
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/*
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* Check for the presence of the Advanced SIMD
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* load/store instructions, integer and single
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* precision floating point operations.
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*/
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if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
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elf_hwcap |= HWCAP_NEON;
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#endif
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}
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return 0;
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}
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late_initcall(vfp_init);
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