255 lines
8.8 KiB
C
255 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*/
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#include "phy-mtk-hdmi.h"
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#include "phy-mtk-io.h"
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#define HDMI_CON0 0x00
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#define RG_HDMITX_PLL_EN BIT(31)
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#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
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#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
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#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
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#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
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#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
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#define RG_HDMITX_PLL_IR GENMASK(15, 12)
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#define RG_HDMITX_PLL_IC GENMASK(11, 8)
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#define RG_HDMITX_PLL_BP GENMASK(7, 4)
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#define RG_HDMITX_PLL_BR GENMASK(3, 2)
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#define RG_HDMITX_PLL_BC GENMASK(1, 0)
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#define HDMI_CON1 0x04
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#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
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#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
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#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
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#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
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#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
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#define RG_HDMITX_PLL_BAND GENMASK(21, 16)
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#define RG_HDMITX_PLL_REF_SEL BIT(15)
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#define RG_HDMITX_PLL_BIAS_EN BIT(14)
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#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
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#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
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#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
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#define RG_HDMITX_PLL_LVROD_EN BIT(9)
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#define RG_HDMITX_PLL_MONVC_EN BIT(8)
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#define RG_HDMITX_PLL_MONCK_EN BIT(7)
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#define RG_HDMITX_PLL_MONREF_EN BIT(6)
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#define RG_HDMITX_PLL_TST_EN BIT(5)
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#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
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#define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0)
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#define HDMI_CON2 0x08
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#define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8)
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#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
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#define RG_HDMITX_EN_TX_CKLDO BIT(0)
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#define HDMI_CON3 0x0c
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#define RG_HDMITX_SER_EN GENMASK(31, 28)
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#define RG_HDMITX_PRD_EN GENMASK(27, 24)
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#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
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#define RG_HDMITX_DRV_EN GENMASK(19, 16)
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#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
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#define RG_HDMITX_MHLCK_FORCE BIT(10)
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#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
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#define RG_HDMITX_MHLCK_EN BIT(8)
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#define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4)
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#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
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#define RG_HDMITX_SER_BIST_TOG BIT(2)
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#define RG_HDMITX_SER_DIN_TOG BIT(1)
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#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
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#define HDMI_CON4 0x10
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#define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24)
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#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
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#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
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#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
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#define HDMI_CON5 0x14
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#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
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#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
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#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
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#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
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#define HDMI_CON6 0x18
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#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
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#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
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#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
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#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
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#define HDMI_CON7 0x1c
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#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
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#define RG_HDMITX_SER_DIN GENMASK(25, 16)
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#define RG_HDMITX_CHLDC_TST GENMASK(15, 12)
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#define RG_HDMITX_CHLCK_TST GENMASK(11, 8)
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#define RG_HDMITX_RESERVE GENMASK(7, 0)
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#define HDMI_CON8 0x20
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#define RGS_HDMITX_2T1_LEV GENMASK(19, 16)
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#define RGS_HDMITX_2T1_EDG GENMASK(15, 12)
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#define RGS_HDMITX_5T1_LEV GENMASK(11, 8)
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#define RGS_HDMITX_5T1_EDG GENMASK(7, 4)
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#define RGS_HDMITX_PLUG_TST BIT(0)
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static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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void __iomem *base = hdmi_phy->regs;
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mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
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mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN);
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mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
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usleep_range(100, 150);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
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usleep_range(100, 150);
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mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
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mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
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return 0;
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}
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static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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void __iomem *base = hdmi_phy->regs;
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mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
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mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
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usleep_range(100, 150);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
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usleep_range(100, 150);
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mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
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mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
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mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
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usleep_range(100, 150);
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}
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static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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hdmi_phy->pll_rate = rate;
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if (rate <= 74250000)
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*parent_rate = rate;
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else
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*parent_rate = rate / 2;
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return rate;
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}
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static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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void __iomem *base = hdmi_phy->regs;
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unsigned int pre_div;
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unsigned int div;
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unsigned int pre_ibias;
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unsigned int hdmi_ibias;
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unsigned int imp_en;
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dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
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rate, parent_rate);
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if (rate <= 27000000) {
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pre_div = 0;
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div = 3;
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} else if (rate <= 74250000) {
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pre_div = 1;
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div = 2;
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} else {
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pre_div = 1;
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div = 1;
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}
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mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div);
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mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
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mtk_phy_update_bits(base + HDMI_CON0,
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RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR,
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FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
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FIELD_PREP(RG_HDMITX_PLL_IR, 0x1));
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mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div);
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mtk_phy_update_bits(base + HDMI_CON0,
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RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV,
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FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
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FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19));
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mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2);
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mtk_phy_update_bits(base + HDMI_CON0,
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RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
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RG_HDMITX_PLL_BR,
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FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
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FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
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FIELD_PREP(RG_HDMITX_PLL_BR, 0x1));
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if (rate < 165000000) {
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mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
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pre_ibias = 0x3;
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imp_en = 0x0;
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hdmi_ibias = hdmi_phy->ibias;
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} else {
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mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
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pre_ibias = 0x6;
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imp_en = 0xf;
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hdmi_ibias = hdmi_phy->ibias_up;
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}
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mtk_phy_update_bits(base + HDMI_CON4,
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RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 |
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RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0,
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
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FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias));
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mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en);
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mtk_phy_update_bits(base + HDMI_CON6,
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RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
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RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0,
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FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
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FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
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FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
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FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0));
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mtk_phy_update_bits(base + HDMI_CON5,
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RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
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RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0,
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
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FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias));
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return 0;
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}
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static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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return hdmi_phy->pll_rate;
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}
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static const struct clk_ops mtk_hdmi_phy_pll_ops = {
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.prepare = mtk_hdmi_pll_prepare,
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.unprepare = mtk_hdmi_pll_unprepare,
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.set_rate = mtk_hdmi_pll_set_rate,
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.round_rate = mtk_hdmi_pll_round_rate,
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.recalc_rate = mtk_hdmi_pll_recalc_rate,
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};
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static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3,
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RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
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RG_HDMITX_DRV_EN);
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usleep_range(100, 150);
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}
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static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3,
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RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
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RG_HDMITX_SER_EN);
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}
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struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
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.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
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.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
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.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
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.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
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};
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MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
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MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
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MODULE_LICENSE("GPL v2");
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