478 lines
11 KiB
C
478 lines
11 KiB
C
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/firmware.h>
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#include <mach/map.h>
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#include "common.h"
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#include "regs-pmu.h"
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extern void exynos4_secondary_startup(void);
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/*
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* Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
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* during hot-(un)plugging CPUx.
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*
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* The feature can be cleared safely during first boot of secondary CPU.
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*
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* Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
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* down a CPU so the CPU idle clock down feature could properly detect global
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* idle state when CPUx is off.
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*/
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static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
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{
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if (soc_is_exynos4()) {
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unsigned int tmp;
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tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
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if (enable)
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tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
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else
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tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
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pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
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}
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static inline void cpu_leave_lowpower(u32 core_id)
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{
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unsigned int v;
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asm volatile(
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"mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, %2\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (CR_C), "Ir" (0x40)
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: "cc");
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exynos_set_delayed_reset_assertion(core_id, false);
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}
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static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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{
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u32 mpidr = cpu_logical_map(cpu);
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u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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for (;;) {
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/* Turn the CPU off on next WFI instruction. */
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exynos_cpu_power_down(core_id);
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/*
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* Exynos4 SoCs require setting
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* USE_DELAYED_RESET_ASSERTION so the CPU idle
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* clock down feature could properly detect
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* global idle state when CPUx is off.
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*/
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exynos_set_delayed_reset_assertion(core_id, true);
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wfi();
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if (pen_release == core_id) {
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/*
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* OK, proper wakeup, we're done
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*/
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break;
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}
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/*
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* Getting here, means that we have come out of WFI without
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* having been woken up - this shouldn't happen
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*
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* Just note it happening - when we're woken, we can report
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* its occurrence.
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*/
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(*spurious)++;
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}
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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/**
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* exynos_core_power_down : power down the specified cpu
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* @cpu : the cpu to power down
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*
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* Power down the specified cpu. The sequence must be finished by a
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* call to cpu_do_idle()
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*
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*/
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void exynos_cpu_power_down(int cpu)
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{
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if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") ||
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of_machine_is_compatible("samsung,exynos5800"))) {
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/*
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* Bypass power down for CPU0 during suspend. Check for
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* the SYS_PWR_REG value to decide if we are suspending
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* the system.
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*/
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int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
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if (!(val & S5P_CORE_LOCAL_PWR_EN))
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return;
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}
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pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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}
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/**
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* exynos_cpu_power_up : power up the specified cpu
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* @cpu : the cpu to power up
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*
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* Power up the specified cpu
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*/
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void exynos_cpu_power_up(int cpu)
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{
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pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
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EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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}
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/**
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* exynos_cpu_power_state : returns the power state of the cpu
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* @cpu : the cpu to retrieve the power state from
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*
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*/
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int exynos_cpu_power_state(int cpu)
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{
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return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
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S5P_CORE_LOCAL_PWR_EN);
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}
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/**
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* exynos_cluster_power_down : power down the specified cluster
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* @cluster : the cluster to power down
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*/
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void exynos_cluster_power_down(int cluster)
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{
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pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
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}
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/**
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* exynos_cluster_power_up : power up the specified cluster
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* @cluster : the cluster to power up
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*/
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void exynos_cluster_power_up(int cluster)
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{
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pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
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EXYNOS_COMMON_CONFIGURATION(cluster));
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}
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/**
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* exynos_cluster_power_state : returns the power state of the cluster
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* @cluster : the cluster to retrieve the power state from
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*
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*/
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int exynos_cluster_power_state(int cluster)
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{
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return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
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S5P_CORE_LOCAL_PWR_EN);
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}
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void __iomem *cpu_boot_reg_base(void)
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{
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
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return pmu_base_addr + S5P_INFORM5;
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return sysram_base_addr;
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}
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static inline void __iomem *cpu_boot_reg(int cpu)
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{
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void __iomem *boot_reg;
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boot_reg = cpu_boot_reg_base();
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if (!boot_reg)
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return ERR_PTR(-ENODEV);
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if (soc_is_exynos4412())
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boot_reg += 4*cpu;
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else if (soc_is_exynos5420() || soc_is_exynos5800())
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boot_reg += 4;
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return boot_reg;
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}
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/*
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* Set wake up by local power mode and execute software reset for given core.
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*
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* Currently this is needed only when booting secondary CPU on Exynos3250.
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*/
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static void exynos_core_restart(u32 core_id)
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{
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u32 val;
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if (!of_machine_is_compatible("samsung,exynos3250"))
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return;
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val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
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val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
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pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
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pr_info("CPU%u: Software reset\n", core_id);
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pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
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}
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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sync_cache_w(&pen_release);
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}
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)(S5P_VA_SCU);
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}
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static DEFINE_SPINLOCK(boot_lock);
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static void exynos_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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u32 mpidr = cpu_logical_map(cpu);
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u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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int ret = -ENOSYS;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU core ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(core_id);
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if (!exynos_cpu_power_state(core_id)) {
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exynos_cpu_power_up(core_id);
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timeout = 10;
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/* wait max 10 ms until cpu1 is on */
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while (exynos_cpu_power_state(core_id)
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!= S5P_CORE_LOCAL_PWR_EN) {
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if (timeout-- == 0)
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break;
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mdelay(1);
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}
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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exynos_core_restart(core_id);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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unsigned long boot_addr;
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smp_rmb();
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boot_addr = virt_to_phys(exynos4_secondary_startup);
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/*
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* Try to set boot address using firmware first
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* and fall back to boot register if it fails.
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*/
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ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
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if (ret && ret != -ENOSYS)
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goto fail;
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if (ret == -ENOSYS) {
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void __iomem *boot_reg = cpu_boot_reg(core_id);
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if (IS_ERR(boot_reg)) {
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ret = PTR_ERR(boot_reg);
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goto fail;
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}
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__raw_writel(boot_addr, boot_reg);
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}
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call_firmware_op(cpu_boot, core_id);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/* No harm if this is called during first boot of secondary CPU */
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exynos_set_delayed_reset_assertion(core_id, false);
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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fail:
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spin_unlock(&boot_lock);
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return pen_release != -1 ? ret : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init exynos_smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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else
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/*
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* CPU Nodes are passed thru DT and set_cpu_possible
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* is set by "arm_dt_init_cpu_maps".
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*/
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return;
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/* sanity check */
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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{
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int i;
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exynos_sysram_init();
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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scu_enable(scu_base_addr());
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/*
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* Write the address of secondary startup into the
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* system-wide flags register. The boot monitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*
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* Try using firmware operation first and fall back to
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* boot register if it fails.
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*/
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for (i = 1; i < max_cpus; ++i) {
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unsigned long boot_addr;
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u32 mpidr;
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u32 core_id;
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int ret;
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mpidr = cpu_logical_map(i);
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core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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boot_addr = virt_to_phys(exynos4_secondary_startup);
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ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
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if (ret && ret != -ENOSYS)
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break;
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if (ret == -ENOSYS) {
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void __iomem *boot_reg = cpu_boot_reg(core_id);
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if (IS_ERR(boot_reg))
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break;
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__raw_writel(boot_addr, boot_reg);
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}
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}
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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static void exynos_cpu_die(unsigned int cpu)
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{
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int spurious = 0;
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u32 mpidr = cpu_logical_map(cpu);
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u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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v7_exit_coherency_flush(louis);
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platform_do_lowpower(cpu, &spurious);
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/*
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* bring this CPU back into the world of cache
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* coherency, and then restore interrupts
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*/
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cpu_leave_lowpower(core_id);
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if (spurious)
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pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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struct smp_operations exynos_smp_ops __initdata = {
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.smp_init_cpus = exynos_smp_init_cpus,
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.smp_prepare_cpus = exynos_smp_prepare_cpus,
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.smp_secondary_init = exynos_secondary_init,
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.smp_boot_secondary = exynos_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = exynos_cpu_die,
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#endif
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};
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