145 lines
3.2 KiB
C
145 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Xilinx, Inc.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/string.h>
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#include <linux/firmware/xlnx-zynqmp.h>
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/* Constant Definitions */
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#define IXR_FPGA_DONE_MASK BIT(3)
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/**
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* struct zynqmp_fpga_priv - Private data structure
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* @dev: Device data structure
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* @flags: flags which is used to identify the bitfile type
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*/
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struct zynqmp_fpga_priv {
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struct device *dev;
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u32 flags;
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};
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static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t size)
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{
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struct zynqmp_fpga_priv *priv;
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priv = mgr->priv;
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priv->flags = info->flags;
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return 0;
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}
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static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
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const char *buf, size_t size)
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{
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struct zynqmp_fpga_priv *priv;
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dma_addr_t dma_addr;
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u32 eemi_flags = 0;
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char *kbuf;
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int ret;
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priv = mgr->priv;
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kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
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if (!kbuf)
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return -ENOMEM;
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memcpy(kbuf, buf, size);
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wmb(); /* ensure all writes are done before initiate FW call */
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if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
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eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
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ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags);
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dma_free_coherent(priv->dev, size, kbuf, dma_addr);
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return ret;
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}
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static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
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{
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u32 status = 0;
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zynqmp_pm_fpga_get_status(&status);
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if (status & IXR_FPGA_DONE_MASK)
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return FPGA_MGR_STATE_OPERATING;
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return FPGA_MGR_STATE_UNKNOWN;
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}
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static ssize_t status_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 status;
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int ret;
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ret = zynqmp_pm_fpga_get_config_status(&status);
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if (ret)
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return ret;
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return sysfs_emit(buf, "0x%x\n", status);
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}
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static DEVICE_ATTR_RO(status);
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static struct attribute *zynqmp_fpga_attrs[] = {
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&dev_attr_status.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(zynqmp_fpga);
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static const struct fpga_manager_ops zynqmp_fpga_ops = {
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.state = zynqmp_fpga_ops_state,
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.write_init = zynqmp_fpga_ops_write_init,
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.write = zynqmp_fpga_ops_write,
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};
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static int zynqmp_fpga_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct zynqmp_fpga_priv *priv;
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struct fpga_manager *mgr;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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mgr = devm_fpga_mgr_register(dev, "Xilinx ZynqMP FPGA Manager",
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&zynqmp_fpga_ops, priv);
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return PTR_ERR_OR_ZERO(mgr);
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}
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#ifdef CONFIG_OF
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static const struct of_device_id zynqmp_fpga_of_match[] = {
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{ .compatible = "xlnx,zynqmp-pcap-fpga", },
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{},
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};
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MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
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#endif
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static struct platform_driver zynqmp_fpga_driver = {
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.probe = zynqmp_fpga_probe,
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.driver = {
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.name = "zynqmp_fpga_manager",
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.of_match_table = of_match_ptr(zynqmp_fpga_of_match),
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.dev_groups = zynqmp_fpga_groups,
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},
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};
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module_platform_driver(zynqmp_fpga_driver);
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MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
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MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
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MODULE_LICENSE("GPL");
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