409 lines
11 KiB
C
409 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (C) 2018 ROHM Semiconductors */
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#ifndef __LINUX_MFD_BD70528_H__
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#define __LINUX_MFD_BD70528_H__
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/mfd/rohm-generic.h>
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#include <linux/regmap.h>
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enum {
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BD70528_BUCK1,
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BD70528_BUCK2,
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BD70528_BUCK3,
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BD70528_LDO1,
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BD70528_LDO2,
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BD70528_LDO3,
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BD70528_LED1,
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BD70528_LED2,
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};
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struct bd70528_data {
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struct rohm_regmap_dev chip;
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struct mutex rtc_timer_lock;
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};
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#define BD70528_BUCK_VOLTS 17
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#define BD70528_BUCK_VOLTS 17
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#define BD70528_BUCK_VOLTS 17
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#define BD70528_LDO_VOLTS 0x20
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#define BD70528_REG_BUCK1_EN 0x0F
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#define BD70528_REG_BUCK1_VOLT 0x15
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#define BD70528_REG_BUCK2_EN 0x10
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#define BD70528_REG_BUCK2_VOLT 0x16
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#define BD70528_REG_BUCK3_EN 0x11
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#define BD70528_REG_BUCK3_VOLT 0x17
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#define BD70528_REG_LDO1_EN 0x1b
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#define BD70528_REG_LDO1_VOLT 0x1e
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#define BD70528_REG_LDO2_EN 0x1c
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#define BD70528_REG_LDO2_VOLT 0x1f
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#define BD70528_REG_LDO3_EN 0x1d
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#define BD70528_REG_LDO3_VOLT 0x20
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#define BD70528_REG_LED_CTRL 0x2b
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#define BD70528_REG_LED_VOLT 0x29
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#define BD70528_REG_LED_EN 0x2a
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/* main irq registers */
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#define BD70528_REG_INT_MAIN 0x7E
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#define BD70528_REG_INT_MAIN_MASK 0x74
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/* 'sub irq' registers */
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#define BD70528_REG_INT_SHDN 0x7F
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#define BD70528_REG_INT_PWR_FLT 0x80
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#define BD70528_REG_INT_VR_FLT 0x81
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#define BD70528_REG_INT_MISC 0x82
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#define BD70528_REG_INT_BAT1 0x83
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#define BD70528_REG_INT_BAT2 0x84
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#define BD70528_REG_INT_RTC 0x85
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#define BD70528_REG_INT_GPIO 0x86
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#define BD70528_REG_INT_OP_FAIL 0x87
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#define BD70528_REG_INT_SHDN_MASK 0x75
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#define BD70528_REG_INT_PWR_FLT_MASK 0x76
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#define BD70528_REG_INT_VR_FLT_MASK 0x77
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#define BD70528_REG_INT_MISC_MASK 0x78
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#define BD70528_REG_INT_BAT1_MASK 0x79
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#define BD70528_REG_INT_BAT2_MASK 0x7a
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#define BD70528_REG_INT_RTC_MASK 0x7b
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#define BD70528_REG_INT_GPIO_MASK 0x7c
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#define BD70528_REG_INT_OP_FAIL_MASK 0x7d
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/* Reset related 'magic' registers */
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#define BD70528_REG_SHIPMODE 0x03
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#define BD70528_REG_HWRESET 0x04
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#define BD70528_REG_WARMRESET 0x05
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#define BD70528_REG_STANDBY 0x06
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/* GPIO registers */
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#define BD70528_REG_GPIO_STATE 0x8F
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#define BD70528_REG_GPIO1_IN 0x4d
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#define BD70528_REG_GPIO2_IN 0x4f
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#define BD70528_REG_GPIO3_IN 0x51
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#define BD70528_REG_GPIO4_IN 0x53
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#define BD70528_REG_GPIO1_OUT 0x4e
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#define BD70528_REG_GPIO2_OUT 0x50
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#define BD70528_REG_GPIO3_OUT 0x52
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#define BD70528_REG_GPIO4_OUT 0x54
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/* clk control */
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#define BD70528_REG_CLK_OUT 0x2c
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/* RTC */
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#define BD70528_REG_RTC_COUNT_H 0x2d
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#define BD70528_REG_RTC_COUNT_L 0x2e
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#define BD70528_REG_RTC_SEC 0x2f
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#define BD70528_REG_RTC_MINUTE 0x30
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#define BD70528_REG_RTC_HOUR 0x31
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#define BD70528_REG_RTC_WEEK 0x32
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#define BD70528_REG_RTC_DAY 0x33
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#define BD70528_REG_RTC_MONTH 0x34
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#define BD70528_REG_RTC_YEAR 0x35
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#define BD70528_REG_RTC_ALM_SEC 0x36
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#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC
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#define BD70528_REG_RTC_ALM_MINUTE 0x37
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#define BD70528_REG_RTC_ALM_HOUR 0x38
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#define BD70528_REG_RTC_ALM_WEEK 0x39
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#define BD70528_REG_RTC_ALM_DAY 0x3a
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#define BD70528_REG_RTC_ALM_MONTH 0x3b
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#define BD70528_REG_RTC_ALM_YEAR 0x3c
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#define BD70528_REG_RTC_ALM_MASK 0x3d
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#define BD70528_REG_RTC_ALM_REPEAT 0x3e
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#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC
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#define BD70528_REG_RTC_WAKE_SEC 0x43
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#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC
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#define BD70528_REG_RTC_WAKE_MIN 0x44
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#define BD70528_REG_RTC_WAKE_HOUR 0x45
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#define BD70528_REG_RTC_WAKE_CTRL 0x46
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#define BD70528_REG_ELAPSED_TIMER_EN 0x42
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#define BD70528_REG_WAKE_EN 0x46
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/* WDT registers */
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#define BD70528_REG_WDT_CTRL 0x4A
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#define BD70528_REG_WDT_HOUR 0x49
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#define BD70528_REG_WDT_MINUTE 0x48
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#define BD70528_REG_WDT_SEC 0x47
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/* Charger / Battery */
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#define BD70528_REG_CHG_CURR_STAT 0x59
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#define BD70528_REG_CHG_BAT_STAT 0x57
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#define BD70528_REG_CHG_BAT_TEMP 0x58
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#define BD70528_REG_CHG_IN_STAT 0x56
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#define BD70528_REG_CHG_DCIN_ILIM 0x5d
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#define BD70528_REG_CHG_CHG_CURR_WARM 0x61
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#define BD70528_REG_CHG_CHG_CURR_COLD 0x62
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/* Masks for main IRQ register bits */
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enum {
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BD70528_INT_SHDN,
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#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
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BD70528_INT_PWR_FLT,
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#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
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BD70528_INT_VR_FLT,
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#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
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BD70528_INT_MISC,
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#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
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BD70528_INT_BAT1,
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#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
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BD70528_INT_RTC,
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#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
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BD70528_INT_GPIO,
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#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
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BD70528_INT_OP_FAIL,
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#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
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};
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/* IRQs */
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enum {
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/* Shutdown register IRQs */
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BD70528_INT_LONGPUSH,
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BD70528_INT_WDT,
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BD70528_INT_HWRESET,
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BD70528_INT_RSTB_FAULT,
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BD70528_INT_VBAT_UVLO,
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BD70528_INT_TSD,
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BD70528_INT_RSTIN,
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/* Power failure register IRQs */
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BD70528_INT_BUCK1_FAULT,
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BD70528_INT_BUCK2_FAULT,
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BD70528_INT_BUCK3_FAULT,
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BD70528_INT_LDO1_FAULT,
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BD70528_INT_LDO2_FAULT,
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BD70528_INT_LDO3_FAULT,
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BD70528_INT_LED1_FAULT,
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BD70528_INT_LED2_FAULT,
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/* VR FAULT register IRQs */
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BD70528_INT_BUCK1_OCP,
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BD70528_INT_BUCK2_OCP,
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BD70528_INT_BUCK3_OCP,
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BD70528_INT_LED1_OCP,
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BD70528_INT_LED2_OCP,
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BD70528_INT_BUCK1_FULLON,
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BD70528_INT_BUCK2_FULLON,
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/* PMU register interrupts */
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BD70528_INT_SHORTPUSH,
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BD70528_INT_AUTO_WAKEUP,
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BD70528_INT_STATE_CHANGE,
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/* Charger 1 register IRQs */
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BD70528_INT_BAT_OV_RES,
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BD70528_INT_BAT_OV_DET,
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BD70528_INT_DBAT_DET,
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BD70528_INT_BATTSD_COLD_RES,
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BD70528_INT_BATTSD_COLD_DET,
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BD70528_INT_BATTSD_HOT_RES,
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BD70528_INT_BATTSD_HOT_DET,
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BD70528_INT_CHG_TSD,
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/* Charger 2 register IRQs */
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BD70528_INT_BAT_RMV,
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BD70528_INT_BAT_DET,
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BD70528_INT_DCIN2_OV_RES,
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BD70528_INT_DCIN2_OV_DET,
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BD70528_INT_DCIN2_RMV,
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BD70528_INT_DCIN2_DET,
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BD70528_INT_DCIN1_RMV,
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BD70528_INT_DCIN1_DET,
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/* RTC register IRQs */
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BD70528_INT_RTC_ALARM,
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BD70528_INT_ELPS_TIM,
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/* GPIO register IRQs */
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BD70528_INT_GPIO0,
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BD70528_INT_GPIO1,
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BD70528_INT_GPIO2,
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BD70528_INT_GPIO3,
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/* Invalid operation register IRQs */
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BD70528_INT_BUCK1_DVS_OPFAIL,
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BD70528_INT_BUCK2_DVS_OPFAIL,
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BD70528_INT_BUCK3_DVS_OPFAIL,
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BD70528_INT_LED1_VOLT_OPFAIL,
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BD70528_INT_LED2_VOLT_OPFAIL,
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};
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/* Masks */
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#define BD70528_INT_LONGPUSH_MASK 0x1
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#define BD70528_INT_WDT_MASK 0x2
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#define BD70528_INT_HWRESET_MASK 0x4
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#define BD70528_INT_RSTB_FAULT_MASK 0x8
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#define BD70528_INT_VBAT_UVLO_MASK 0x10
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#define BD70528_INT_TSD_MASK 0x20
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#define BD70528_INT_RSTIN_MASK 0x40
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#define BD70528_INT_BUCK1_FAULT_MASK 0x1
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#define BD70528_INT_BUCK2_FAULT_MASK 0x2
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#define BD70528_INT_BUCK3_FAULT_MASK 0x4
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#define BD70528_INT_LDO1_FAULT_MASK 0x8
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#define BD70528_INT_LDO2_FAULT_MASK 0x10
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#define BD70528_INT_LDO3_FAULT_MASK 0x20
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#define BD70528_INT_LED1_FAULT_MASK 0x40
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#define BD70528_INT_LED2_FAULT_MASK 0x80
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#define BD70528_INT_BUCK1_OCP_MASK 0x1
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#define BD70528_INT_BUCK2_OCP_MASK 0x2
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#define BD70528_INT_BUCK3_OCP_MASK 0x4
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#define BD70528_INT_LED1_OCP_MASK 0x8
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#define BD70528_INT_LED2_OCP_MASK 0x10
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#define BD70528_INT_BUCK1_FULLON_MASK 0x20
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#define BD70528_INT_BUCK2_FULLON_MASK 0x40
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#define BD70528_INT_SHORTPUSH_MASK 0x1
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#define BD70528_INT_AUTO_WAKEUP_MASK 0x2
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#define BD70528_INT_STATE_CHANGE_MASK 0x10
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#define BD70528_INT_BAT_OV_RES_MASK 0x1
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#define BD70528_INT_BAT_OV_DET_MASK 0x2
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#define BD70528_INT_DBAT_DET_MASK 0x4
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#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
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#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
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#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
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#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
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#define BD70528_INT_CHG_TSD_MASK 0x80
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#define BD70528_INT_BAT_RMV_MASK 0x1
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#define BD70528_INT_BAT_DET_MASK 0x2
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#define BD70528_INT_DCIN2_OV_RES_MASK 0x4
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#define BD70528_INT_DCIN2_OV_DET_MASK 0x8
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#define BD70528_INT_DCIN2_RMV_MASK 0x10
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#define BD70528_INT_DCIN2_DET_MASK 0x20
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#define BD70528_INT_DCIN1_RMV_MASK 0x40
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#define BD70528_INT_DCIN1_DET_MASK 0x80
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#define BD70528_INT_RTC_ALARM_MASK 0x1
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#define BD70528_INT_ELPS_TIM_MASK 0x2
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#define BD70528_INT_GPIO0_MASK 0x1
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#define BD70528_INT_GPIO1_MASK 0x2
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#define BD70528_INT_GPIO2_MASK 0x4
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#define BD70528_INT_GPIO3_MASK 0x8
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#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
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#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
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#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
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#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
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#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20
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#define BD70528_DEBOUNCE_MASK 0x3
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#define BD70528_DEBOUNCE_DISABLE 0
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#define BD70528_DEBOUNCE_15MS 1
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#define BD70528_DEBOUNCE_30MS 2
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#define BD70528_DEBOUNCE_50MS 3
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#define BD70528_GPIO_DRIVE_MASK 0x2
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#define BD70528_GPIO_PUSH_PULL 0x0
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#define BD70528_GPIO_OPEN_DRAIN 0x2
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#define BD70528_GPIO_OUT_EN_MASK 0x80
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#define BD70528_GPIO_OUT_ENABLE 0x80
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#define BD70528_GPIO_OUT_DISABLE 0x0
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#define BD70528_GPIO_OUT_HI 0x1
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#define BD70528_GPIO_OUT_LO 0x0
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#define BD70528_GPIO_OUT_MASK 0x1
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#define BD70528_GPIO_IN_STATE_BASE 1
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#define BD70528_CLK_OUT_EN_MASK 0x1
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/* RTC masks to mask out reserved bits */
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#define BD70528_MASK_RTC_SEC 0x7f
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#define BD70528_MASK_RTC_MINUTE 0x7f
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#define BD70528_MASK_RTC_HOUR_24H 0x80
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#define BD70528_MASK_RTC_HOUR_PM 0x20
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#define BD70528_MASK_RTC_HOUR 0x1f
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#define BD70528_MASK_RTC_DAY 0x3f
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#define BD70528_MASK_RTC_WEEK 0x07
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#define BD70528_MASK_RTC_MONTH 0x1f
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#define BD70528_MASK_RTC_YEAR 0xff
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#define BD70528_MASK_RTC_COUNT_L 0x7f
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#define BD70528_MASK_ELAPSED_TIMER_EN 0x1
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/* Mask second, min and hour fields
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* HW would support ALM irq for over 24h
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* (by setting day, month and year too)
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* but as we wish to keep this same as for
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* wake-up we limit ALM to 24H and only
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* unmask sec, min and hour
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*/
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#define BD70528_MASK_ALM_EN 0x7
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#define BD70528_MASK_WAKE_EN 0x1
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/* WDT masks */
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#define BD70528_MASK_WDT_EN 0x1
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#define BD70528_MASK_WDT_HOUR 0x1
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#define BD70528_MASK_WDT_MINUTE 0x7f
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#define BD70528_MASK_WDT_SEC 0x7f
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#define BD70528_WDT_STATE_BIT 0x1
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#define BD70528_ELAPSED_STATE_BIT 0x2
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#define BD70528_WAKE_STATE_BIT 0x4
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/* Charger masks */
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#define BD70528_MASK_CHG_STAT 0x7f
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#define BD70528_MASK_CHG_BAT_TIMER 0x20
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#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10
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#define BD70528_MASK_CHG_BAT_DETECT 0x1
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#define BD70528_MASK_CHG_DCIN1_UVLO 0x1
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#define BD70528_MASK_CHG_DCIN_ILIM 0x3f
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#define BD70528_MASK_CHG_CHG_CURR 0x1f
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#define BD70528_MASK_CHG_TRICKLE_CURR 0x10
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/*
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* Note, external battery register is the lonely rider at
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* address 0xc5. See how to stuff that in the regmap
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*/
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#define BD70528_MAX_REGISTER 0x94
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/* Buck control masks */
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#define BD70528_MASK_RUN_EN 0x4
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#define BD70528_MASK_STBY_EN 0x2
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#define BD70528_MASK_IDLE_EN 0x1
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#define BD70528_MASK_LED1_EN 0x1
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#define BD70528_MASK_LED2_EN 0x10
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#define BD70528_MASK_BUCK_VOLT 0xf
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#define BD70528_MASK_LDO_VOLT 0x1f
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#define BD70528_MASK_LED1_VOLT 0x1
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#define BD70528_MASK_LED2_VOLT 0x10
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/* Misc irq masks */
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#define BD70528_INT_MASK_SHORT_PUSH 1
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#define BD70528_INT_MASK_AUTO_WAKE 2
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#define BD70528_INT_MASK_POWER_STATE 4
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#define BD70528_MASK_BUCK_RAMP 0x10
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#define BD70528_SIFT_BUCK_RAMP 4
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#if IS_ENABLED(CONFIG_BD70528_WATCHDOG)
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int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state);
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void bd70528_wdt_lock(struct rohm_regmap_dev *data);
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void bd70528_wdt_unlock(struct rohm_regmap_dev *data);
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#else /* CONFIG_BD70528_WATCHDOG */
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static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
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int *old_state)
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{
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return 0;
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}
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static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
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{
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}
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static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
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{
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}
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#endif /* CONFIG_BD70528_WATCHDOG */
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#endif /* __LINUX_MFD_BD70528_H__ */
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